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Senior Physical Design Engineer

Ciena

Ottawa, ON

Full-time

Utilize tools like Formality or Conformal for formal verification, analyzing reports and ensuring design accuracy and integrity.

ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal

Celero Communications, Inc.

Ottawa, ON

Perform synthesis, timing analysis, lint, formal equivalence, Clock Domain Crossing (CDC), and related ASIC implementation and signoff activities.