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Advanced Micro Devices, Inc

ASIC Verification Engineer, AI Networking IP

84 Hines Rd Suite #300, Ottawa, ON, K2K 3G3, Canada

Full-time

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Job details

Job type: Full-time
Apply by: Oct 23, 2027
Posting language: English
Posted: Oct 23, 2026

Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

We are looking for a talented ASIC Verification Engineer to join our team of experts, developing high-performance networking and communications IP for advanced AMD products. You’ll work with a highly motivated team of engineers developing best-in-class verification environments for leading edge AI networking and communications silicon.

THE PERSON:

You want to develop yours skills in ASIC verification and digital design and join a world class team. You have a passion for continous improvement, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

Contribute to the development of advanced, re-usable verification environments and IP components
Investigate and root cause issues found during the IP development stage
Write tests, sequences, and testbench components in SystemVerilog and UVM to verify the design
Employ a Coverage-Driven Verification methodology with Constrained Random Stimulus
Contribute to process improvements via automation of tasks and exploring and evaluating new tools and methodologies
Drive formal verification for the block and write formal properties and assertions to verify the design

PREFERRED EXPERIENCE:

Understanding of digital design principles
Understanding of Object Oriented Coding practices
Experience with SystemVerilog, C or C++ programming languages
Experience with agentic coding tools such as Claude Code or Codex
Experience with Python, Perl or other scripting languages is an asset

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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More about this job

Responsibilities

The engineer will contribute to the development of advanced, reusable verification environments and IP components for AI networking silicon. Responsibilities include writing tests and sequences in SystemVerilog/UVM, performing root cause analysis, and driving formal verification.

Requirements

Candidates should have a Bachelor's or Master's degree in Computer or Electrical Engineering with a strong understanding of digital design and object-oriented coding. Proficiency in SystemVerilog, C/C++, and scripting languages like Python or Perl is required.

Skills

ASIC Verification
SystemVerilog
UVM
Digital Design
C
C++
Python
Perl
Constrained Random Stimulus
Coverage-Driven Verification
Formal Verification
Object Oriented Programming
Networking IP
Problem-solving
Communication skills

Visa sponsorship

Not detected in the job text

Keywords

ASIC
Verification
AI Networking
IP Development
SystemVerilog
UVM
Digital Design
C
C++
Python
Perl
Constrained Random Stimulus
Coverage-Driven Verification
Formal Verification
Object Oriented Programming
Automation
Silicon
Claude Code
Codex
Computer Engineering
Electrical Engineering

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