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Added 1 min ago
Reliability Engineer
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Added 1 min ago
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Added 14 mins ago
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Added 16 mins ago
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Added 44 mins ago
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Advanced Micro Devices, Inc

Custom Layout Design Engineer

1 Commerce Valley Drive, Markham, ON, L3T 7X6, Canada

Job type: Temporary
Apply by: Sep 21, 2027
Posting language: English
Posted: Sep 21, 2026

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Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

The Full Custom IC Layout team is seeking an engineer to design and implement layouts for digital and analog circuits based on schematics using industry-standard CAD tools and advanced semiconductor process technologies. Examples of layouts developed by our team include high-speed I/O drivers and receivers, delay lines, duty-cycle correction (DCC) circuits, calibration circuits, clock buffers, and custom digital circuits.

This team plays a critical role in enabling AMD's next-generation semiconductor products. Team members collaborate across multiple engineering disciplines to solve complex technical challenges and contribute to innovative solutions used by customers worldwide. In this role, you will have the opportunity to work on impactful technologies while developing expertise in advanced process nodes, custom layout methodologies, and physical design verification.

THE PERSON:

In this role, you will contribute across multiple phases of the design lifecycle, from initial floor planning and routing of lower-level logic gates through top-level integration, verification, and tape out activities. Day-to-day responsibilities include creating lower-level cell layouts and assembling them into larger IP blocks. You will use a variety of verification tools throughout the design hierarchy, including DRC, LVS, EM/IR, ERC, and Latch-up/ESD verification. As you grow in the role, you may also collaborate with and help coordinate work across globally distributed engineering teams and external design partners.

KEY RESPONSIBILITIES:

Create high-quality, manufacturable layouts for digital and analog building blocks at the transistor level using Cadence Virtuoso.
Floorplan, route, and assemble lower-level cells into macros.
Build black-box and abstract models consumed by other teams and contribute to tape out collateral for custom blocks.
Run hierarchical verification at the cell and macro levels (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and drive issue resolution in collaboration with circuit designers.
Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality.

PREFERRED EXPERIENCE:

Experience in custom IC layout design is preferred. Candidates with relevant industry, research, internship, or project experience are encouraged to apply.
Demonstrated understanding of CMOS device and circuit theory, as well as analog and digital layout best practices.
Experience using industry-standard layout tools such as Cadence Virtuoso and Calibre.
Experience with LVS, DRC, EMIR, and other physical verification methodologies.
Exposure to advanced process nodes (e.g., 2nm, 3nm, 5nm, or 7nm technologies).
Experience with IP or standard-cell layout, high-speed differential signaling, PLL/DLL/VCO circuits, DACs, power pads, and in-context XOR verification.
Experience with scripting or automation using Perl, TCL, SVRF/TVF, SKILL, or similar languages is a plus.

ACADEMIC CREDENTIALS:

Bachelor’s or master’s degree in Electrical Engineering, Mechanical Engineering, Electronics, or a related technical field.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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More about this job

Responsibilities

The engineer will design and implement layouts for digital and analog circuits using industry-standard CAD tools and advanced semiconductor process technologies. Responsibilities include floorplanning, routing, hierarchical verification, and collaborating with cross-functional teams to ensure manufacturability.

Requirements

Candidates should have a bachelor's or master's degree in Electrical Engineering or a related field and experience with custom IC layout design. Proficiency in tools like Cadence Virtuoso and Calibre, along with a strong understanding of CMOS device theory and physical verification methodologies, is required.

Skills

Custom IC Layout
Cadence Virtuoso
Calibre
DRC
LVS
EM/IR
ERC
Latch-up/ESD
CMOS Device Theory
Circuit Theory
Floorplanning
Routing
Physical Design Verification
Scripting
Automation

Visa sponsorship

Not detected in the job text

Keywords

Custom IC Layout
Cadence Virtuoso
Calibre
DRC
LVS
EM/IR
ERC
Latch-up
ESD
CMOS
Floorplanning
Routing
Semiconductor
Perl
TCL
SVRF
TVF
SKILL
Analog Circuits
Digital Circuits
High-speed I/O
PLL
DLL
VCO
DAC
Physical Design
Tape out
Automation
Scripting
IP Blocks

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