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Added 51 mins ago
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Advanced Micro Devices, Inc

IOHUB Design Verification Engineer

1 Commerce Valley Drive, Markham, ON, L3T 7X6, Canada

Full-time

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Job details

Job type: Full-time
Apply by: Oct 9, 2027
Posting language: English
Posted: Oct 9, 2026

Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

The Role

The AMD NBIO (North Bridge I/O) team delivers industry-leading, high-performance interconnect IP for AMD products, including discrete GPUs, machine learning products, APUs, servers, and game consoles. The global NBIO organization operates seamlessly across China, North America, and Europe.

IOHUB sits at the center of the system’s data paths. It includes two foundational IP blocks, IOHUB Core and IOMMU, as well as the IOHUB. IOHUB Core is the system’s PCI host bridge and provides decoding and routing services to PCIe and other devices. The IOMMU (I/O Memory Management Unit) is responsible for address translation and memory protection. It plays a critical role in I/O virtualization technology, which is widely used in hyperscale data centers.

The Person

The successful candidate will work closely with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, with strong communication and problem-solving skills.

Demonstrates strong teamwork
Drives work through completion

Key Responsibilities

Define the IOHUB verification strategy and scope.
Develop the IOHUB test plan, implement DRVR, and drive verification closure.
Work closely with the Design and Architecture teams to develop new verification components.
Organize and attend conference calls with global teams for strategy alignment, status synchronization, and related activities.

Preferred Experience

Experience working in a global company and fluency in spoken English.
Experience with complex IP, ASIC, or SoC design verification. Direct experience with IP/SoC development, processors such as CPUs or GPUs, or industry bus standards such as PCIe or HT is preferred.
Good knowledge of UVM, Verilog, SystemC, and SystemVerilog.
Solid knowledge of hardware verification methodologies, including coverage-based verification, hardware assertions such as PSL or SVA, and constrained-random techniques.
Experience with verification planning is an asset.
Knowledge of virtualization is an asset.
Experience developing with AI assistants is a plus.
Strong collaboration skills.

Academic Credentials

Master’s degree in electrical engineering and digital ASIC or SoC design verification experience, or
Bachelor’s degree in electrical engineering and digital ASIC or SoC design verification experience.

Location:

Markham, ON or Vancouver, BC

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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More about this job

Responsibilities

Define the IOHUB verification strategy and scope while developing comprehensive test plans. Collaborate with design and architecture teams to implement verification components and drive verification closure.

Requirements

Requires a Bachelor's or Master's degree in electrical engineering with experience in digital ASIC or SoC design verification. Candidates should possess strong knowledge of UVM, Verilog, SystemVerilog, and industry bus standards like PCIe.

Skills

Design Verification
UVM
Verilog
SystemVerilog
SystemC
PCIe
IOMMU
Hardware Assertions
PSL
SVA
Constrained-random Techniques
Verification Planning
ASIC Design
SoC Design
Communication Skills
Problem-solving

Visa sponsorship

Not detected in the job text

Keywords

IOHUB
Design Verification
ASIC
SoC
UVM
Verilog
SystemVerilog
SystemC
PCIe
HT
IOMMU
PCI Host Bridge
Virtualization
Coverage-based Verification
PSL
SVA
Constrained-random
Verification Planning
Hardware Engineering
North Bridge I/O
Data Paths
Address Translation
Memory Protection
AI Assistants

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