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Added 9 mins ago
SL
Digital Product Manager - CRM and Partnerships
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- Full-time
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Added 24 mins ago
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Senior Azure Cloud Platform Engineer -- KUMDC6125986
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Advanced Micro Devices, Inc

IP-Post Silicon Validation Engineer

2930 Virtual Way Ste. 300, Vancouver, BC, V5M 4X6, Canada

Full-time

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Job details

Job type: Full-time
Apply by: Nov 5, 2027
Posting language: English
Posted: Nov 5, 2026

Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:
The AMD NBIO Team is on the lookout for a seasoned IP Validation Design Engineer to join our growing team. As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and validation in general. You are a team player who has excellent communication skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. You are a self-starter with strong analytical and problem-solving skills and are willing to learn and ready to independently drive tasks to completion.

KEY RESPONSIBILITIES:
As an IP Validation Design Engineer, you will drive the planning, validation, and debug of various hardware IP for forthcoming AMD APU, CPU, Compute and Discrete Graphics SOC programs.

Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power
Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements
Defining, documenting, executing and reporting the overall functional test plan and end to end validation strategy for a set of AMD IP’s.
Driving technical innovation to enhance AMD's capabilities in IP validation, including tools and scripts/automation development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives.
Debugging IP issues found during pre-silicon, bring-up, system validation, and production phases of the SOC programs.
Engaging on pre-silicon ‘shift left’ activities with cross-functional teams such as Design Verification (DV), Diagnostics, Emulation and other software/hardware modeling frameworks to ensure readiness for first silicon arrival, enablement of IP functionality, and debug of critical features.
Leading collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives.
Developing knowledge of system architecture/debug and other internal IP’s.
Supporting issues on customer platforms as required by customer engineering teams.

PREFERRED EXPERIENCE:

Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, High Speed I/O subsystems, Clocks, Resets, Virtualization and Security
Experience in digital logic design/verification/post-silicon validation.
Extensive experience with ASIC debug techniques and methodologies.
Knowledge of physical and protocol levels of common high-speed interfaces an asset.
Experience with board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization.
Strong scripting skills (eg. Ruby, Python).
Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.
In-depth knowledge of IOMMU IP architecture is an asset.
Excellent communication, management, and presentation skills.
Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
Leadership and mentoring skills a definite asset.
Must be a self-starter and be able to independently drive tasks to completion.

ACADEMIC CREDENTIALS:

Bachelor’s or Master’s degree majoring in EE, CS or related field.

LOCATION: Markham

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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More about this job

Responsibilities

The engineer will drive the planning, validation, and debug of hardware IP for AMD's APU, CPU, and discrete graphics SOC programs. They will work cross-functionally to ensure alignment between hardware, firmware, BIOS, and software while developing validation strategies and automation tools.

Requirements

Candidates must have a bachelor's or master's degree in EE, CS, or a related field with a strong foundation in SoC architecture and digital design. Extensive experience in ASIC debug, scripting, and lab equipment usage is required, along with excellent communication and leadership skills.

Skills

SoC architecture
Post-silicon validation
Digital logic design
ASIC debug
Python
Ruby
Protocol analyzers
Oscilloscopes
IOMMU
System architecture
Hardware validation
Firmware
BIOS
Automation
Technical leadership
Mentoring

Visa sponsorship

Not detected in the job text

Keywords

SoC
IP Validation
Post-silicon
CPU
GPU
APU
ASIC
Firmware
BIOS
Python
Ruby
IOMMU
Digital Logic
System Architecture
Automation
Debug
Hardware
Memory Sub-system
High Speed I/O
Virtualization
Security
Protocol Analyzers
Oscilloscopes
Shift Left
Emulation
Diagnostics
Technical Innovation
Cross-functional Collaboration
Mentoring
Leadership

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