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Advanced Micro Devices, Inc

Memory PHY - Technical Lead

1 Commerce Valley Drive, Markham, ON, L3T 7X6, Canada

Full-time

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Job details

Job type: Full-time
Apply by: Oct 28, 2027
Posting language: English
Posted: Oct 28, 2026

Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

Implementation and verification of DFT architecture and features

Scan insertion and ATPG pattern generation
ATPG patterns verification with gate-level simulation
Test coverage and test cost reduction analysis
Post silicon support to ensure successful bring up and enhance yield learning

PREFERRED EXPERIENCE:

Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION:

Markham, Ontario, Canada ( Open to Vancouver, BC and Ottawa,ON)

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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More about this job

Responsibilities

The role involves implementing and verifying DFT architecture, including scan insertion and ATPG pattern generation. Additionally, the candidate will perform test coverage analysis and provide post-silicon support to ensure successful product bring-up and yield improvement.

Requirements

Candidates must have a Bachelor's or Master's degree in Computer or Electrical Engineering. Proficiency in DFT methodologies, simulation tools like VCS, and scripting languages such as Perl or Shell is required.

Skills

DFT architecture
Scan insertion
ATPG pattern generation
Gate-level simulation
Test coverage analysis
Memory BIST
IEEE1500
JTAG 1149.x
Mentor Testkompress
Synopsys Tetramax
DFTMAX
VCS simulation
Perl
Shell scripting
Verilog RTL design

Visa sponsorship

Not detected in the job text

Keywords

Memory PHY
Technical Lead
DFT
Design for Test
Silicon Design
Radeon Technologies Group
RTL Design
Verilog
VCS
Perl
Shell Scripting
ATPG
Scan Insertion
Memory BIST
IEEE1500
JTAG
Mentor Testkompress
Synopsys Tetramax
DFTMAX
Gate-level Simulation
Post Silicon Support
Yield Learning
Computer Engineering
Electrical Engineering
Semiconductor

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