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Advanced Micro Devices, Inc

RTL Design Engineer

33 Commerce Valley Drive, Markham, ON, L3T 7N6, Canada

Full-time

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Job details

Job type: Full-time
Apply by: Oct 9, 2027
Posting language: English
Posted: Oct 9, 2026

Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:
An RTL Design Engineering role in our Security IP (SECIP) team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators vital to improve subsystems performance and functionality are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our design engineers will work on block level RTL design and/or subsystem level integration for a variety of embedded MP subsystems. Your expertise will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications.

THE PERSON:

A talented hardware RTL design engineer with strong records of technical ownership and execution to drive block level IP and/or MP subsystems design and associated verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability.

KEY RESPONSIBILITIES:

Develop and maintain block level RTL IP and MP subsystems’ feature spec, micro-architecture, synthesizable RTL design methodology and infrastructure
Develop and debug RTL designs using C-DPI directed test methodology, and/or using verification team’s testbenches and tests, and achieve design feature closure (feature spec vs. coverage metrics)
Triage regressions, debug specific simulations, analyze coverage, and work/resolve technical issues with design, verification, and other teams to achieve design feature and design rule closures (linting, timing, DFT, DFP and other rules)
Participate in verification testbench and test plan specification, influence testbench architecture development (design for verification aspect), review and improve feature and coverage test plans
Develop and execute the IP integration flow, coordinate IP release collaterals within the IP teams
Debug and resolve integration issues with SoC Integration, SoC DV and post-silicon validation teams

PREFERRED EXPERIENCE:

Excellent understanding of CPU and MP subsystem architecture, datapath accelerator RTL microarchitecture, as well as FPGA based simulation or emulation methodology
Proficient in Verilog, System Verilog (an extra asset), and scripting (using Tcl, Ruby, Perl, Python and Makefile)
Excellent knowledge about state-of-art RTL design and verification methodology and best practices, and C-DPI test design
Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
Proven experience with ASIC design tools: synthesis, linting, simulation, debugging, power aware simulation, etc.

ACADEMIC CREDENTIALS:

Bachelor's Degree or Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field
Master's Degree preferred

LOCATION: Markham, ON ( Open to Austin, TX)

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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More about this job

Responsibilities

Develop and maintain block-level RTL IP and MP subsystems, including feature specifications and micro-architecture design. Coordinate IP integration flows and resolve technical issues with SoC integration and validation teams.

Requirements

Requires a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science. Candidates must have strong experience in RTL design, verification methodologies, and standard bus protocols like AXI and AHB.

Skills

RTL Design
Verilog
System Verilog
C-DPI
Micro-architecture
AXI
AHB
AMBA
Tcl
Ruby
Perl
Python
Makefile
ASIC Design Tools
FPGA Emulation
Debugging

Visa sponsorship

Not detected in the job text

Keywords

RTL Design
Security IP
Micro-processor
Hardware Accelerators
SoC
Cryptography
DMA
Power Management
Verilog
System Verilog
C-DPI
AXI
AHB
AMBA
Tcl
Ruby
Perl
Python
Makefile
ASIC
FPGA
Synthesis
Linting
Simulation
Debugging
Power Aware Simulation
DFT
DFP
Regression
Coverage Metrics

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