Silicon Design Engineer
- 1 Commerce Valley Drive, Markham, ON, L3T 7X6, Canada
Full-time
Applications open in a new tab.
Job details
- Job type
- Full-time
- Apply by
- Posting language
- English
- Posted
Original job description
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.
SILICON DESIGN ENGINEER 2
THE ROLE:
As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the Physical Design team, you will work closely with the architecture, IP design, front-end design/integration teams, and product engineers to achieve first pass silicon success.
THE PERSON:
A successful candidate will work with senior silicon design engineers. The candidate will be accurate and detail-oriented, possessing good communication and problem-solving skills.
KEY RESPONSIBLITIES:
- Knowledge and experience in Physical design and apply them to large, challenging, leading-edge designs to ensure high quality on time delivery.
- Understand Full Chip Physical Verification, architecture and work with the team to drive floorplan related activities. Handle complex partitions, TSV, advanced process node rules.
- Technically assist with different aspects of Physical Design including Chip Level Floor planning, Bus / Pin Planning, repeaters, feedthroughs.
- Coordinate with STA, EMIR and FCFP teams to drive floorplan changes.
- Help assist in flow development and scripting.
- Strong analytical and problem solving skills.
PREFERRED EXPERIENCE:
- 1-2+ years of Experience in ASIC Physical Design in latest process nodes.
- Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics required.
- Must be a self-starter and able to independently and efficiently drive challenging and time critical tasks to on-time completion.
- Understand Full Chip Physical Verification and architecture and work with the team to drive physical verification related activities. Handle complex partitions, TSV, advanced process node rules.
- Understanding of Place & route, Timing Analysis, clock tree distribution, Physical Verification, Chip Integration.
- Experience with tcl/Perl/Shell scripting.
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
More about this job
Responsibilities
The candidate will work within the Physical Design team to drive floorplan activities, chip-level integration, and physical verification for leading-edge silicon designs. They will coordinate with cross-functional teams including architecture, STA, and EMIR to ensure high-quality, on-time delivery of complex partitions.
Requirements
The role requires 1-2+ years of experience in ASIC physical design using industry-standard CAD tools from Synopsys, Cadence, and Mentor Graphics. Candidates must possess a Bachelor's or Master's degree in Computer or Electrical Engineering and demonstrate strong problem-solving skills.
Skills
- ASIC Physical Design
- Floorplanning
- Physical Verification
- Chip Integration
- Timing Analysis
- Clock Tree Distribution
- Place & Route
- Tcl
- Perl
- Shell Scripting
- Synopsys
- Cadence
- Mentor Graphics
- TSV
- Bus Planning
- Pin Planning
Visa sponsorship
Not detected in the job text
Categories
- Engineering
- Technology
- Software
Keywords
- Silicon Design
- ASIC
- Physical Design
- Radeon Technologies Group
- Floorplanning
- Physical Verification
- Chip Integration
- STA
- EMIR
- FCFP
- TSV
- Process Nodes
- Synopsys
- Cadence
- Mentor Graphics
- Tcl
- Perl
- Shell Scripting
- Timing Analysis
- Clock Tree Distribution
- Place & Route
- Computer Engineering
- Electrical Engineering
- Semiconductor
- Processor Design