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Added 1 month ago
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Advanced Micro Devices, Inc

Sr. Systems Design Engineer - Data Center GPU

1 Commerce Valley Drive, Markham, ON, L3T 7X6, Canada

Full-time

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Job details

Job type: Full-time
Apply by: Aug 20, 2027
Posting language: English
Posted: Aug 20, 2026

Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger - technology that moves the world forward.

THE ROLE:

We are looking for a dynamic, energetic Sr. Systems Design Engineer to join our growing Data Center GPU team. As a key contributor to the success of AMD’s product, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry-leading technologies to market. The Systems Design Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON:

In this role, you will drive balanced, scalable, and automated solutions. In this high visibility position, your software systems engineering expertise will be necessary towards Product development, definition, and root cause resolution.

KEY RESPONSIBILITIES:

Executing and contributing to post-silicon validation efforts for SOC-level IP blocks, including test plan development, test execution, coverage tracking, and issue reporting across program milestones
Debugging hardware and system-level issues found during bring-up, validation, and production phases of SOC programs, with a focus on system IP blocks such as DMA engines, interrupt controllers, and data path logic
Performing post-silicon debug analysis using scan dump tools and debug reports to investigate hangs, stalls, and error conditions at the IP and system level
Triaging failures by collecting and correlating debug data across multiple IP domains, with guidance from senior engineers on complex cross-chiplet issues
Working with multiple teams and tracking test execution to make sure all features are validated and optimized on time
Working closely with design, firmware, driver, software runtime, and kernel teams to understand IP behavior, error propagation, software-hardware interactions, and power management dependencies
Developing and maintaining validation test content targeting error handling, fault injection, and power management scenarios
Engaging in hardware/software modeling and debug frameworks to reproduce and root-cause silicon failures
Participating in collaborative triage and debug efforts across multiple teams and IP domains, progressively taking ownership of specific IP areas

PREFERRED EXPERIENCE:

Experience in post-silicon validation, hardware debug, or a related semiconductor engineering role
Programming/scripting skills (e.g., C/C++, Python, Perl)
Debug techniques and methodologies for post-silicon validation
Experience with board/platform-level debugging, including bring-up, sequencing, analysis, and optimization
Knowledge of SoC system architecture, including multi-die or chiplet-based designs
Understanding of cache hierarchies, buffer allocation and management, ring buffers, FIFO structures, credit-based flow control, and tag tracking mechanisms
Familiarity with DMA, interrupt handling, memory subsystem, or I/O subsystem architectures
Knowledge of memory management concepts including address translation, virtual memory, TLB operation, and page fault handling
Familiarity with software runtime environments, kernel-level drivers, or OS-level interfaces that interact with hardware IPs
Exposure to RAS concepts - error detection, poison propagation, machine check logging, and watchdog mechanisms
Experience with scan dump analysis or JTAG-based post-silicon debug tools
Strong analytical/problem-solving skills and pronounced attention to detail
Must be a self-starter, able to independently drive tasks to completion and willing to ramp up on new IP domains through documentation and hands-on debug

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in electrical or computer engineering

LOCATION:

Markham, ON

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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More about this job

Responsibilities

The role involves executing post-silicon validation for SOC-level IP blocks and debugging hardware issues found during bring-up and production. You will collaborate with cross-functional teams to triage failures and optimize system features.

Requirements

Candidates should have experience in post-silicon validation, hardware debug, and proficiency in programming languages like C++ or Python. A bachelor's or master's degree in electrical or computer engineering is required.

Skills

Post-silicon validation
Hardware debug
C++
Python
Perl
SoC architecture
DMA
Interrupt handling
Memory subsystem
I/O subsystem
RAS concepts
Scan dump analysis
JTAG
Firmware
Kernel-level drivers
Chiplet design

Visa sponsorship

Not detected in the job text

Keywords

Data Center GPU
Post-silicon validation
SoC
IP blocks
DMA
Interrupt controllers
Data path logic
Scan dump
Chiplet
Cache hierarchies
Ring buffers
FIFO
Credit-based flow control
Address translation
Virtual memory
TLB
Page fault
RAS
Poison propagation
Machine check logging
Watchdog
JTAG
Firmware
Kernel-level drivers
Power management
C++
Python
Perl
Hardware debug
Supercomputing

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