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STA/Constraints Engineer
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Vancouver, BC
Full-time
The STA/Constraints Engineer is responsible for developing FullChip constraints and timing closure. Person will work closely with Fellows, Principal Engineers, Architects, collaborate with…

Advanced Micro Devices, Inc

STA/Constraints Engineer

2930 Virtual Way Ste. 300, Vancouver, BC, V5M 4X6, Canada

Job type: Full-time
Apply by: Sep 30, 2027
Posting language: English
Posted: Sep 30, 2026

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Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

The STA/Constraints Engineer is responsible for developing FullChip constraints and timing closure. Person will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers.

KEY RESPONSIBILITIES:

Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective.
Work closely with the SOC Architecture team for SOC clocks & STA for statistical timing target goals.
Understanding clock design requirements and making sure they are correctly set up in SDC.
Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects.
Understand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.
Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology.
Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.
Work on SDC development, STA (Static Timing) analysis, shift left of timing closure, CDC (Clock Domain Crossing).

PREFERRED EXPERIENCE:

Industry experience in STA, constraints and timing signoff.
Expert user of industry-standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired).
Good experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.
Excellent presentation and inter-communication skills.
Experience with Verilog RTL design/implementation and has experience of large digital ASIC project.
Experience with physical design is a plus.
Has Synthesis or physical implement experience.
Experience with lower power design methodology.
Good English skills on talking, presentation and writing documents.
Good communication and strong sense of responsibility, task scheduling, and time management.

ACADEMIC CREDENTIALS:

Bachelor/Master’s degree in Micro Electronics/ Integrated Circuit Science, or related field preferred.

LOCATION: Vancouver, BC

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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More about this job

Responsibilities

The STA/Constraints Engineer is responsible for developing full-chip constraints and ensuring timing closure for SOC and sub-system integration. They will collaborate with cross-functional teams including architecture, physical design, and CAD to deliver high-quality netlists and timing signoff.

Requirements

Candidates must have industry experience in STA, constraints, and timing signoff, along with expertise in industry-standard PD tools. A bachelor's or master's degree in Microelectronics, Integrated Circuit Science, or a related field is preferred.

Skills

STA
Constraints
Timing closure
Physical design
Synthesis
Perl
TCL
Shell
Python
Verilog
RTL design
CDC
SNPS PT
GCA
ICC2
FC

Visa sponsorship

Not detected in the job text

Keywords

STA
Constraints
Timing closure
SOC
Physical design
Synthesis
Timing signoff
SDC
CDC
RTL design
Perl
TCL
Python
Verilog
SNPS PT
GCA
ICC2
FC
Low power design
Micro electronics
Integrated circuit science
Digital ASIC
LVF
SSTA
Variations
Netlist quality
CAD
EDA
Shift left
FullChip

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