Jobs in King, ON and nearby

Jobs within 25 km of King, ON, Canada. Nearby towns and cities are included. Distances are straight-line, not driving distances.

6,437 listings · 1,395 employers Counted Oct 4, 2026. How we count

About these jobs

Employers hiring include Loblaw Companies Limited (124 listings), Advanced Micro Devices, Inc (99 listings), Walmart Canada (92 listings).

Common roles: Retail sales associate, Personal support worker, Sales representative.

808 of these listings include employer-provided pay. Open a job to see its currency and pay period.

Advertised starting pay
Pay period	Median starting pay	Listings
CAD / year	75,000.00	375
CAD / hour	22.26	342
USD / year	75,000.00	26
USD / hour	20.00	16

Employer-listed minimums from at least 10 listings per currency and pay period. These are advertised starting amounts, not employee salaries. Jobs without a minimum and unusual amounts are excluded.

Workplace classifications: 0% remote, 14% hybrid, 86% on-site, 0% not specified. Hybrid and on-site classifications may be inferred from descriptions. Check the original ad.

Based on the dated count above. Listings can change. How we count

Jobs in King, ON and nearby

Within 25 km

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Added 3 days ago
FB
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- $18 CAD / hour
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HM
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- $55,000 to $65,000 CAD / year
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TR
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C
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Richmond Hill, ON
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Concord, ON
- Full-time
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M
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- $200,000 to $230,000 CAD / year
- Full-time
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Vaughan, ON
- $55,000 to $70,000 CAD / year
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G
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GL
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3
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YH
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- $56,014 to $58,323 CAD / year
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YH
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- $68,080 to $74,000 CAD / year
- Full-time
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Added 3 days ago
Manager, Contract
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Vaughan, ON

Advanced Micro Devices, Inc

Static Timing Analysis / Full Chip Timing Engineer

33 Commerce Valley Drive, Markham, ON, L3T 7N6, Canada

Full-time

Apply About employer

Applications open in a new tab.

Job details

Job type: Full-time
Apply by: Sep 24, 2027
Posting language: English
Posted: Sep 24, 2026

Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

ROLE SUMMARY:

Own full-chip static timing analysis (STA) and timing closure for complex SoC designs, from

early design netlist through final signoff. Partner closely with PnR, synthesis/DFT, and CAD

teams to drive timing convergence, methodology improvements, and flow automation across the

business unit.

KEY RESPONSIBILITIES:

Timing Closure & Signoff

Own full-chip timing closure across setup, hold, and DRV (transition/capacitance/noise) signoff

Drive multi-corner/multi-mode (MMMC) timing convergence across PVT corners and modes

Analyze and resolve SI/crosstalk, OCV/POCV, and clock-related (skew, jitter, uncertainty) impacts on timing

Perform root-cause analysis of timing violations and drive fixes through ECO, PnR trials etc.

Generate, validate, and hand off ECOs to PnR PD teams; verify legalization and post-ECO QoR

Clock Architecture

Guide clock tree build strategy across multiple methodologies (H-tree, MSCTS/multi-source CTS, clock mesh)

Define clock structure and skew/latency targets in partnership with clock architecture and PD teams

Cross-Team Collaboration

Work with PnR engineers to drive timing convergence at each implementation stage (place, CTS, route, ECO)

Provide SDC (constraint) analysis, quality review, and feedback to design and synthesis teams

Feed back repeater/floorplan/design guidance across SoC based on timing analysis

Analyze run data and provide actionable feedback to PD execution teams

Collaborate across business units, CAD, and central methodology teams to define and drive requirements

Interface with other PPA (or equivalent) teams internal to AMD on cross-cutting timing topics

Methodology & Automation

Define and drive common STA methodology and signoff criteria across the business unit

Build automation to streamline design signoff checks, QoR tracking, and dashboard generation

Identify and adopt best practices from across AMD and industry to continuously improve flow/project best practices

Drive stage-by-stage improvements in competitiveness (PPA, turnaround time) of the AMD design flow

Communication

Organize and present complex technical timing data clearly and concisely to technical and management audiences

Document methodology, flows, and known issues for broader team consumption

REQUIRED QUALIFICATIONS:

BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field

Full chip timing experience preferred

Location:

Markham, ON

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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More about this job

Responsibilities

The engineer will own full-chip static timing analysis and timing closure for complex SoC designs from netlist to final signoff. They will collaborate with PnR, synthesis, and CAD teams to drive timing convergence, methodology improvements, and flow automation.

Requirements

Candidates must hold a BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field. Experience in full-chip timing analysis is preferred.

Skills

Static Timing Analysis
SoC Design
Timing Closure
Signoff
PnR
Synthesis
DFT
CAD
MMMC
PVT
SI/Crosstalk
OCV/POCV
Clock Tree Synthesis
SDC
ECO
PPA

Visa sponsorship

Not detected in the job text

Keywords

Static Timing Analysis
SoC
Timing Closure
Signoff
PnR
Synthesis
DFT
CAD
MMMC
PVT
SI
Crosstalk
OCV
POCV
Clock Tree Synthesis
H-tree
MSCTS
Clock Mesh
SDC
ECO
PPA
Automation
Electrical Engineering
Computer Engineering
Semiconductor
Processor Design
AI
QoR

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