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Added 1 month ago
Q
GPU Compiler Engineer - Multiple Levels
Qualcomm
Markham, ON
- Full-time
…create a smarter, connected future for all. As a Qualcomm GPU Engineer, you may architect, design, implement, verify, and/or optimize the performance and power of GPU cores. Qualcomm…
Added 1 month ago
Q
Physical Design Engineer
Qualcomm
Markham, ON
- Full-time
Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
Added 1 month ago
WA
MLOps Engineer, LLM Systems (Serving, GPU Kernels, Profiling)
Weekday AI
Remote, Canada
- Part-time
- Remote
Develop guidelines and detailed rubrics or evaluation frameworks covering kernel-level optimization, profiler output interpretation, distributed systems reasoning, and serving throughput…
Added 1 month ago
Senior Mobile Programmer
Epic Games
Montreal, QC
The Fortnite Technology Team is looking for an experienced Mobile Platform Engineer passionate about creating world-class, industry leading game engine technologies, targeting the full…
Added 1 month ago
Software Dev Engineer, Machine Learning Compilers, Edge AI Compiler and Runtime Team
Amazon
Vancouver, BC
You join a small team building the compiler that brings large AI models to a new generation of custom silicon. The chip has a fraction of the memory of a phone, and the compiler is what…
Added 1 month ago
Q
Engineer - Machine Learning Software
Qualcomm
Markham, ON
- Full-time
Use cross compiler toolchains for embedded systems such as Android, embedded Linux and QNX
Added 1 month ago
Senior ML Kernel Performance Engineer
Amazon
Toronto, ON
Our kernel engineers collaborate across compiler, runtime, framework, and hardware teams to optimize machine learning workloads for our global customer base. Working at the intersection of…
Added 2 months ago
SI
Principal Physical Design Methodology Engineer
Synopsys Inc
Markham, ON
- Full-time
Deep expertise with Fusion Compiler or equivalent industry synthesis and place-and-route tools (ICC2, Innovus), including advanced features like multi-mode multi-corner optimization, clock…
Added 1 month ago
IC
Triton Compiler Engineer
Intel Corporation
ON · Virtual - CAN ON
- Full-time
Experience with compiler stages, code generation, and optimization techniques
Added 1 month ago
IC
Compiler Engineer
Intel Corporation
ON · Virtual - CAN ON
- Full-time
We are hiring a Compiler Engineer to work on Intel's open-source compiler stack. You will work on the development of new features that will enable the latest language standards. This work…
Added 2 months ago
MT
Software Engineer
Microchip Technology Inc.
Toronto, ON
- Full-time
We currently have an opening for a Software Engineer on our team. In this role, you will play a key part in shaping the future of FPGA design tools. Your primary focus will be compiler…
Added 4 months ago
AM
3D IC and ADVANCED PACKAGING CAD ENGINEER
Advanced Micro Devices, Inc
Markham, ON
- Full-time
…element creation, port assignment and pattern generation, tile optimization, clock and power distribution, high-performance bus implementation, and timing budgeting. We evaluate, procure,…
Added 2 months ago
FM
Software Development (Embedded) Engineer
Ford Motor Company
Ottawa, ON · Kanata, ON
- Full-time
Drive performance optimization across RAM usage, CPU load, and compiler/build settings.
Added 2 months ago
SS
AI Performance Engineer – GPU & ROCm
Sapphire Stream Technology
Toronto, ON
- Full-time
We are looking for a GPU AI Performance Engineer to optimize and deploy AI and machine-learning workloads using ROCm.
Added 4 months ago
HT
Co-op Engineer - Compiler
Huawei Technologies Canada Co., Ltd.
Ottawa, ON · Markham, ON
- Internship
Huawei Canada has an immediate co-op opening for an Engineer.
Added 2 months ago
A
FPGA Compiler (Placer) Engineer
Altera
Toronto, ON
- Full-time
Altera is seeking a FPGA Compiler Engineer (Placer) to join our Compiler team in Toronto, Ontario Canada. This role focuses on developing and optimizing FPGA placement algorithms within the…
Added 2 months ago
R
SMTS Logic Design
Rambus
Montreal, QC
- Other
…exceptional Senior Member of Technical Staff (SMTS) – Logic Design Engineer to join our PCIe Switch Architecture and Design team in Montreal, Canada. In this role, you will be working with…
Added 2 months ago
Q
Senior Embedded Software Engineer (C/C++), Machine Learning
Qualcomm
Markham, ON
- Full-time
…operators to low level hardware instructions, involving various optimization techniques: graph transformation, scheduling, memory planning, individual operator implementation, quantization,…
Added 2 months ago
Q
AI/Machine Learning Engineer (Embedded Systems, Inference Efficiency)
Qualcomm
Markham, ON
- Full-time
Conduct cutting-edge research in inference efficiency and ML system optimization: efficient architecture design, model compression, PEFT, compiler stack optimization etc.
Added 4 months ago
BP
Software Engineering (Compilers / LLVM / MLIR / Runtime)
Botic Partners
Bluewater, Ontario · Zurich, ON
- Full-time
Job Description: Software Engineer – Compilers & Runtime Systems
Added 5 months ago
HC
Co-op Engineer - Compiler
Huawei Canada
Markham, Ontario
- Full-time
Huawei Canada has an immediate co-op opening for an Engineer.
Added 1 month ago
A
CPU Performance Engineer
AMD
Markham, ON
- $128,000 to $192,000 USD / year
- Full-time
…microprocessor architects, ISA definition owners, software optimizers, compiler team, logic designers, and verification engineers to identify, resolve and document architectural performance…
Added 3 months ago
A
FPGA Development Tools Engineer
Altera
Toronto, ON
- Full-time
Familiarity with compiler concepts (parsing, code generation, optimization) through coursework or personal projects.
Added 1 month ago
ML Systems Software Development Engineer Intern, Annapurna Labs - 2027
Amazon
Toronto, ON
…engineering, profiling, benchmarking, or low-level systems optimization. 2/ Kernel development, parallel programming, or computer architecture. 3/ Developer tooling, including profilers,…
Added 3 months ago
MT
Senior Engineer - Software
Microchip Technology Inc.
Toronto, ON
- Full-time
As a Software Engineer on our team, you will play a pivotal role in shaping the future of FPGA design tools. Your primary focus will be on compiler development (LLVM/MLIR-based), with…

Altera

FPGA Compiler (Placer) Engineer

Toronto, ON, Canada

Full-time

Apply About employer

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Job details

Job type: Full-time
Experience: 6+ years of experience in FPGA/ASIC CAD, EDA tools, or related fields.
Posting language: English
Posted: Aug 3, 2026

Original job description

Job Details:

Job Description:

About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely - empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

Position Overview

Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are central to enabling customers to efficiently map complex designs onto advanced FPGA architectures.

Altera is seeking a FPGA Compiler Engineer (Placer) to join our Compiler team in Toronto, Ontario Canada. This role focuses on developing and optimizing FPGA placement algorithms within the compiler toolchain, directly impacting performance, power efficiency, and overall design quality.

The ideal candidate brings strong expertise in EDA algorithms, large-scale system optimization, and FPGA/ASIC physical design flows, along with a passion for solving complex, performance-critical problems.

Key Responsibilities:

Placement Algorithm Development:
Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization.
Compiler Flow Enhancement:
Contribute to the end-to-end FPGA compilation flow, working closely with routing, synthesis, and timing teams.
Performance Optimization:
Improve runtime performance, scalability, and quality of results (QoR) for large and complex customer designs.
Timing-Driven Placement:
Develop and refine timing-aware placement strategies to support high-frequency, performance-critical designs.
Cross-Functional Collaboration:
Partner with architecture, routing, and STA teams to align placement strategies with FPGA device capabilities and constraints.
Debug & Analysis:
Analyze placement quality, congestion hotspots, and timing bottlenecks; drive improvements to convergence and design closure.
Toolchain Integration:
Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.

Why Join Altera?

Work on core compiler technology that directly impacts FPGA performance and usability
Solve challenging algorithmic problems at scale
Collaborate with world-class teams across architecture, silicon, and software

Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position’s location, as well as the candidate’s experience, skills, training, and job-specific knowledge. In addition to base salary, we offer performance-based incentive opportunities that reward both individual contributions and overall company success.

Estimated Salary Range: $129.1 – $187.0 CAD

We use artificial intelligence to screen, assess, or select applicants for the position. This posting is for an existing vacancy. Canadian work experience is not required for this role. Applicants must be eligible for any required Canada export authorizations.

Qualifications:

Minimum Qualifications:

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
6+ years of experience in FPGA/ASIC CAD, EDA tools, or related fields.
Experience in algorithms and data structures (optimization, graph theory, heuristics)
Experience with placement algorithms or physical design flows
Experience in C/C++ and software engineering best practices
Experience with placement techniques (analytical placement, simulated annealing, partitioning, clustering)
Experience with Timing-driven and congestion-driven optimization
Experience in ASIC or FPGA physical design methodologies
Experience in solving complex, large-scale optimization problems with high performance and scalability requirements.

Preferred Qualifications

Experience with FPGA toolchains (e.g., Quartus, Vivado)
Knowledge of FPGA architectures and interconnect fabrics
Familiarity with routing and timing closure techniques
Experience with parallel or distributed algorithms for EDA tools
Scripting experience (e.g., Python, Tcl) for tooling and automation

Job Type:

Regular

Shift:

Shift 1 (Canada)

Primary Location:

Toronto, Ontario, Canada

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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More about this job

Responsibilities

Develop and optimize FPGA placement algorithms to improve timing, congestion, and resource utilization within the compiler toolchain. Collaborate with cross-functional teams to enhance the end-to-end compilation flow and ensure high-quality design closure.

Requirements

Requires a Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. Candidates must have 6+ years of experience in FPGA/ASIC CAD or EDA tools, with strong proficiency in C/C++ and physical design methodologies.

Skills

FPGA
Compiler design
Placement algorithms
C++
EDA tools
Physical design
Timing closure
Congestion analysis
Graph theory
Heuristics
Optimization
Python
Tcl
ASIC
Quartus
Vivado

Benefits

Performance-based incentive opportunities

Visa sponsorship

Not detected in the job text

Keywords

FPGA
Compiler
Placer
EDA
C++
Physical Design
Timing-driven placement
Graph theory
Heuristics
Quartus
Vivado
Python
Tcl
ASIC
Algorithm development
Scalability
Performance optimization
Interconnect fabrics
STA
Software engineering
Design closure
Analytical placement
Simulated annealing
Clustering
Partitioning
Compiler infrastructure
Toolchain
Hardware architecture
Optimization

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