FPGA IP Design Engineer - PEY Intern

Job Details:

Job Description:

This internship is considered a PEY internship at our Toronto location with the expected start and end dates: May 3, 2027 - August 31, 2028.

About the Role

Altera is hiring a FPGA IP Design Engineer - Intern! As modern FPGAs become increasingly like a SoC, Altera's IP Engineering teams develop comprehensive solutions to provide customers easy and efficient access to the capabilities of Altera's FPGA devices. We build IP cores to enable Memory Subsystems using External Memory Interfaces (like DDR5, LPDDR5) or High Bandwidth Memory (HBM) over a high speed NOC.

These IP cores provide configurable access to these high-speed, high-bandwidth memory devices. Most customers require some form of packet processing, storage or buffering, and thus, these IP cores become a critical component of most electronic systems.

The constantly rising speed and complexity of memory devices and interfaces presents a challenging design problem that requires system level knowledge of silicon, software, IP, and customer applications.

As an IP Design Engineer, you will work with a team of engineers to develop and verify state-of-the-art Memory Interface or NoC-based IP cores. You will be working on advanced device architectures, design definition, implementation, and verification. You will also be developing design examples and simulation models, accompanied by a rich set of technical documentation.

Your specific responsibilities will include, but are not limited to the following:

• Architecture and Design based on the latest protocol specifications for memory, or NoC RTL development
• Device support and CAD tool integration
• Verification (e.g. verification IP, methodologies, frameworks, bus functional models, regression tests)
• Hardware power-on and debug
• New product release and rollout support
• Customer technical support

The candidate should possess the following behavioral traits:

• Strong skills in communication, initiative, innovation, and teamwork
• Highly motivated to learn and adapt to fast-changing technologies and environments
• Excellent problem-solving skills and attention to detail
• Demonstrate fundamental values such as accountability, integrity, and a winning mindset
• Collaborative mindset, strong influencing skills, and a willingness to work across geographical locations.

Salary

Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position’s location, as well as the candidate’s experience, skills, training, and job-specific knowledge.

Estimated Salary Range: $90,000 - $100,000 CAD

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We use artificial intelligence to screen, assess, or select applicants for the position.​ This posting is for an existing vacancy.​ Canadian work experience is not required for this role. Applicants must be eligible for any required Canada export authorizations.

Qualifications:

Minimum Qualifications

The candidate must be pursuing a Bachelor's Degree in computer engineering, electrical engineering, engineering science, computer science, mathematics, or similar and 3+ months of experience or coursework in one, or more, of the following:

• Software programming and/or scripting (e.g. C/C++, Python), digital logic, RTL design (e.g. SystemVerilog, Verilog, VHDL), or similar

Preferred Qualifications

• FPGA design experience, Experience with RTL simulation, timing closure, STA, Experience with Memory Interfaces.

Job Type:

Student / Intern (Fixed Term)

Shift:

Shift 1 (Canada)

Primary Location:

Toronto, Ontario, Canada

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.