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Added 13 hours ago
AM
IOHUB Design Verification Engineer
Advanced Micro Devices, Inc
Markham, ON
- Full-time
Experience with complex IP, ASIC, or SoC design verification. Direct experience with IP/SoC development, processors such as CPUs or GPUs, or industry bus standards such as PCIe or HT is…
Added 13 hours ago
AM
RTL Design Engineer
Advanced Micro Devices, Inc
Markham, ON
- Full-time
We are seeking a highly motivated RTL IP Design Engineer to join AMD's Security IP (SECIP) Design team. The team is responsible for the architecture, design, and verification of a broad…
Added 13 hours ago
AM
Senior ASIC RTL Design Engineer, AI Networking IP
Advanced Micro Devices, Inc
Ottawa, ON
- Full-time
We are looking for a talented ASIC RTL Design Engineer to join our IP design team developing high-performance networking and communications IP for advanced AMD products. Our intellectual…
Added 18 hours ago
A
Senior ASIC RTL Design Engineer, AI Networking IP
AMD
Ottawa, ON · Kanata, ON
- $128,000 to $192,000 USD / year
- Full-time
We are looking for a talented ASIC RTL Design Engineer to join our IP design team developing high-performance networking and communications IP for advanced AMD products. Our intellectual…
Added 18 hours ago
Q
ASIC/FPGA Design Verification Engineer, Senior
Qualcomm
Ottawa, ON
- Full-time
Senior ASIC/FPGA Design Verification Engineer
Added 18 hours ago
Q
IC/FPGA Design Verification Engineer, Sr Staff
Qualcomm
Ottawa, ON
- Full-time
Senior Staff ASIC/FPGA Design Verification Engineer
Added 1 day ago
A
IOHUB Design Verification Engineer
AMD
Markham, ON
- $128,000 to $192,000 USD / year
- Full-time
Experience with complex IP, ASIC, or SoC design verification. Direct experience with IP/SoC development, processors such as CPUs or GPUs, or industry bus standards such as PCIe or HT is…
Added 2 days ago
AM
Principal ASIC Design Engineer
Advanced Micro Devices, Inc
Markham, ON
- Full-time
The IOHUB team at AMD is seeking a Principal ASIC Design Engineer to provide technical leadership for the development of next-generation IP that enables AMD products across server, data…
Added 4 days ago
MC
Senior ASIC Verification Engineer (35885)
Myticas Consulting
Ottawa, ON · Kanata, ON
- Full-time
Work as an independent contributor in the development and verification of advanced SoCs based on the latest ASIC and FPGA technologies. The role involves developing robust verification…
Added 5 days ago
T®
Circuit Design Engineer - Senior
TekWissen ®
Vaughan, ON
- $55 to $57 CAD / hour
- Contract
Experience with ASIC EDA tools used in synthesis, place and route, simulation, static timing analysis, test insertion, and formal verification.
Added 8 days ago
C
Senior Physical Design Engineer
Ciena
Ottawa, ON
- Full-time
…and success in the telecommunications industry. As a Digital ASIC Physical Implementation Engineer, you will play a critical role in developing large mixed-signal SoC ASICs targeting…
Added 9 days ago
ASIC Digital Design, Principal Engineer-18731
Synopsys
Mississauga, ON
You are an experienced ASIC Verification Engineer with a strong track record of delivering high-quality mixed-signal IP products, especially high-speed SerDes-based PHYs. You bring deep…
Added 9 days ago
Project Engineering Management, Principal Engineer
Synopsys
Mississauga, ON
…self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to…
Added 9 days ago
H
Staff Systems Engineer, Signal Processing/SAR Processor for Fastwater Staffing and Recruiting
HIKINEX
Remote, Canada
- Contract
- Remote
Our client is hiring a Staff-level engineer to lead a highly specialized team building cutting-edge, high-throughput signal processing systems that turn raw satellite radar data into SAR…
Added 9 days ago
AM
Sr. Physical Design Engineer, Place & Route Lead
Advanced Micro Devices, Inc
Markham, ON
- Full-time
…high-performance computing products on advanced process technologies. As a Senior Physical Design Engineer, you will lead physical implementation activities for complex designs, driving…
Added 10 days ago
A
Sr. Physical Design Engineer, Place & Route Lead
AMD
Markham, ON
- $155,200 to $232,800 USD / year
- Full-time
…high-performance computing products on advanced process technologies. As a Senior Physical Design Engineer, you will lead physical implementation activities for complex designs, driving…
Added 10 days ago
DT
Senior Design Verification Engineer
Diligent Tec, Inc
Vancouver, BC
- Contract
We are looking for a Design Verification Engineer with strong experience in ASIC/SoC verification to develop and execute verification environments and ensure high-quality digital designs.
Added 10 days ago
C
Senior ASIC Verification Engineer, onsite Kanata
Ciena
Ottawa, ON
- $109,000 to $174,000 CAD / year
- Full-time
…strengthen our team, we are looking for a hardworking digital verification engineer who will be involved in the verification of these products, working within a team of digital design…
Added 11 days ago
Senior ASIC (Front End) Design Engineer
Ethernovia, Inc.
Toronto, ON
As a Senior ASIC (Front End) Design Engineer, you will be responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC,…
Added 16 days ago
C
Senior FPGA Verification Engineer
Ciena
Ottawa, ON
- Full-time
Experience: 8+ years of experience as an FPGA/ASIC verification engineer.
Added 17 days ago
SI
ASIC Digital Design, Principal Engineer-18731
Synopsys Inc
Mississauga, ON
- Full-time
You are an experienced ASIC Verification Engineer with a strong track record of delivering high-quality mixed-signal IP products, especially high-speed SerDes-based PHYs. You bring deep…
Added 18 days ago
C
Senior Physical Design Engineer
Ciena
Ottawa, ON
- Full-time
…and success in the telecommunications industry. As a Digital ASIC Physical Implementation Engineer, you will play a critical role in developing large mixed-signal SoC ASICs targeting…
Added 18 days ago
Q
GPU Compiler Engineer - Multiple Levels
Qualcomm
Markham, ON
- Full-time
…create a smarter, connected future for all. As a Qualcomm GPU Engineer, you may architect, design, implement, verify, and/or optimize the performance and power of GPU cores. Qualcomm…
Added 23 days ago
AM
RTL Design Engineer
Advanced Micro Devices, Inc
Markham, ON
- Full-time
As a RTL Design Engineer on the T&E NBIO/PCIe Subsystem team, you will help bring cutting-edge silicon designs to life. You will contribute to RTL and IP logic design while collaborating…
Added 1 month ago
T
Senior Specialist UT Systems Engineer
Telesat
Ottawa, ON · Greater Ottawa Metropolitan Area
- Full-time
The Senior Specialist User Terminal Systems Engineer will provide technical expertise in the development of equipment, software and systems related to the development of LEO Lightspeed user…

AMD

IOHUB Design Verification Engineer

Markham, ON, Canada

$128,000 to $192,000 USD / year · Full-time

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Job details

Pay: $128,000 to $192,000 USD / year
Job type: Full-time
Apply by: Nov 8, 2026
Posting language: English
Posted: Oct 9, 2026

Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

The Role

The AMD NBIO (North Bridge I/O) team delivers industry-leading, high-performance interconnect IP for AMD products, including discrete GPUs, machine learning products, APUs, servers, and game consoles. The global NBIO organization operates seamlessly across China, North America, and Europe.

IOHUB sits at the center of the system’s data paths. It includes two foundational IP blocks, IOHUB Core and IOMMU, as well as the IOHUB. IOHUB Core is the system’s PCI host bridge and provides decoding and routing services to PCIe and other devices. The IOMMU (I/O Memory Management Unit) is responsible for address translation and memory protection. It plays a critical role in I/O virtualization technology, which is widely used in hyperscale data centers.

The Person

The successful candidate will work closely with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, with strong communication and problem-solving skills.

Demonstrates strong teamwork
Drives work through completion

Key Responsibilities

Define the IOHUB verification strategy and scope.
Develop the IOHUB test plan, implement DRVR, and drive verification closure.
Work closely with the Design and Architecture teams to develop new verification components.
Organize and attend conference calls with global teams for strategy alignment, status synchronization, and related activities.

Preferred Experience

Experience working in a global company and fluency in spoken English.
Experience with complex IP, ASIC, or SoC design verification. Direct experience with IP/SoC development, processors such as CPUs or GPUs, or industry bus standards such as PCIe or HT is preferred.
Good knowledge of UVM, Verilog, SystemC, and SystemVerilog.
Solid knowledge of hardware verification methodologies, including coverage-based verification, hardware assertions such as PSL or SVA, and constrained-random techniques.
Experience with verification planning is an asset.
Knowledge of virtualization is an asset.
Experience developing with AI assistants is a plus.
Strong collaboration skills.

Academic Credentials

Master’s degree in electrical engineering and digital ASIC or SoC design verification experience, or
Bachelor’s degree in electrical engineering and digital ASIC or SoC design verification experience.

Location:

Markham, ON or Vancouver, BC

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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More about this job

Responsibilities

Define the IOHUB verification strategy and scope, develop the test plan, implement the driver, and drive verification to closure. Collaborate with design, architecture, and global teams to develop verification components and align on strategy and status.

Requirements

Requires a master's degree in electrical engineering with digital ASIC or SoC design verification experience, or a bachelor's degree in electrical engineering with such experience. Candidates should have experience with complex IP, ASIC, or SoC verification and knowledge of UVM, Verilog, SystemC, SystemVerilog, coverage-based methods, assertions, and constrained-random techniques; PCIe, processor, virtualization, and AI-assistant experience are advantageous.

Skills

Design Verification
Verification Planning
UVM
Verilog
SystemC
SystemVerilog
Coverage-Based Verification
Hardware Assertions
PSL
SVA
Constrained-Random Verification
PCIe
IOMMU
Virtualization
Problem-Solving
Collaboration

Visa sponsorship

Not detected in the job text

Keywords

AMD
NBIO
IOHUB
IOHUB Core
IOMMU
Design Verification
Verification Strategy
Verification Planning
Test Plan
DRVR
IP
ASIC
SoC
CPU
GPU
PCIe
HT
UVM
Verilog
SystemC
SystemVerilog
Coverage-Based Verification
PSL
SVA
Constrained-Random Techniques
Virtualization
I/O Memory Management
Address Translation
Memory Protection
AI Assistants

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