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Added 6 mins ago
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Added 38 mins ago
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AMD

Principal ASIC Design Engineer

Markham, ON, Canada

$155,200 to $232,800 USD / year · Full-time

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Job details

Pay: $155,200 to $232,800 USD / year
Job type: Full-time
Apply by: Nov 4, 2026
Posting language: English
Posted: Oct 5, 2026

Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE

The IOHUB team at AMD is seeking a Principal ASIC Design Engineer to provide technical leadership for the development of next-generation IP that enables AMD products across server, data center, client, and embedded markets. As a senior member of the team, you will help define and deliver innovative technologies that manage and optimize AI-driven data movement, enabling industry-leading performance, scalability, security, virtualization, and power efficiency.

In this role, you will collaborate with architecture, design, verification, firmware, implementation, and product teams across AMD to transform complex product requirements into robust silicon solutions. You will have the opportunity to influence technical strategy, drive architectural innovation, mentor engineers, and help shape engineering best practices that support AMD's future generations of AI and high-performance computing products.

THE PERSON

You are a collaborative and technically influential engineering leader who thrives in solving complex design challenges and driving execution across multidisciplinary teams. You combine strong architectural judgment with a practical, results-oriented approach to problem solving and are comfortable making decisions in ambiguous environments.

You are passionate about mentoring engineers, elevating technical quality, and promoting scalable design methodologies. You communicate effectively across organizations, build alignment among stakeholders, and demonstrate ownership in driving challenging technical issues to closure. You also embrace emerging technologies, including AI-enabled engineering tools, to enhance productivity, design quality, and development efficiency.

Key Responsibilities

Provide technical leadership and ownership for critical IOHUB IP development, ensuring successful execution from architecture through tape-out and post-silicon validation.
Partner with architecture teams to evaluate technical trade-offs, define requirements, and translate product objectives into scalable and high-quality design solutions.
Drive design quality and implementation readiness by ensuring designs meet functional, timing, area, power, security, and reliability goals.
Lead cross-functional collaboration among architecture, design, verification, firmware, physical design, and product teams to achieve program milestones and successful product delivery.
Identify technical risks, dependencies, and integration challenges early, and develop effective mitigation and execution strategies.
Establish and promote engineering best practices that improve design quality, reuse, efficiency, maintainability, and long-term scalability.
Mentor and guide engineers through architecture reviews, implementation challenges, debug activities, and technical decision-making processes.
Drive successful post-silicon bring-up, validation, and root-cause analysis activities to support product quality and continuous improvement.
Communicate technical direction, project status, risks, and key decisions effectively to engineering leadership and stakeholders across global teams.
Champion the adoption of innovative methodologies, including AI-assisted workflows and automation, to enhance engineering effectiveness and development velocity.

Preferred Experience

Proven track record of leading significant ASIC or silicon design contributions through multiple successful product tape-outs.
Deep expertise in RTL design, microarchitecture development, and complex IP design within advanced SoC environments.
Experience developing high-performance designs that address power, performance, security, scalability, and virtualization requirements.
Strong understanding of industry-standard simulation, lint, CDC, RDC, formal verification, static analysis, synthesis, and timing closure methodologies.
Experience collaborating across architecture, design verification, implementation, firmware, and post-silicon engineering organizations.
Proficiency with Verilog, SystemVerilog, and scripting languages such as Python, Perl, or Tcl for design automation and productivity improvements.
Experience leveraging AI-enabled tools to improve design workflows, automation, analysis, debug, documentation, or engineering productivity.
Demonstrated ability to lead technical reviews, influence design decisions, and drive complex technical issues to resolution.
Strong written and verbal communication skills with the ability to present technical information to engineering and leadership audiences.
Demonstrated technical leadership, ownership, accountability, and commitment to engineering excellence.

ACADEMIC CREDENTIALS

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field preferred.
Master's degree or Ph.D. in a related technical discipline desired.

LOCATION:

Markham, Ontario, Canada

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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More about this job

Responsibilities

Provide technical leadership and ownership for IOHUB IP development from architecture through tape-out and post-silicon validation, ensuring designs meet functional, performance, power, security, and reliability goals. Lead cross-functional execution, mentor engineers, manage technical risks, establish design best practices, and promote AI-assisted workflows and automation.

Requirements

The role seeks a senior ASIC design leader with a proven record of significant silicon contributions through multiple product tape-outs and deep expertise in RTL, microarchitecture, and complex SoC IP. Candidates should be proficient in Verilog or SystemVerilog and design automation scripting, understand verification and implementation methodologies, and demonstrate technical leadership, collaboration, and strong communication skills; a bachelor's degree is preferred, with a master's degree or Ph.D. desired.

Skills

ASIC Design
RTL Design
Microarchitecture
IP Design
Verilog
SystemVerilog
Python
Perl
Tcl
Simulation
Lint
CDC
RDC
Formal Verification
Synthesis
Timing Closure

Visa sponsorship

Not detected in the job text

Keywords

ASIC
Silicon Design
IOHUB
IP Development
RTL
Microarchitecture
SoC
Verilog
SystemVerilog
Python
Perl
Tcl
Simulation
Lint
CDC
RDC
Formal Verification
Static Analysis
Synthesis
Timing Closure
Tape-Out
Post-Silicon Validation
AI-Assisted Workflows
Design Automation
Power, Performance, Area
Security
Virtualization
Firmware
Physical Design
Root-Cause Analysis

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