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Contract
About the Job Senior DevOps Engineer (alternate: Senior Cloud / Platform Engineer) About the role:

AMD

Silicon Design Engineer

Markham, ON, Canada

Pay: $91,200 to $136,800 USD / year
Job type: Full-time
Apply by: Oct 28, 2026
Posting language: English
Posted: Sep 28, 2026

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Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

The Role

This is an ASIC Verification Engineering role within the Security IP Team (SECIP). The role focuses on co-verification of embedded microprocessor subsystems and associated hardware accelerators in leading-edge SoCs. The ideal candidate will also contribute to firmware development initiatives supporting high-performance subsystems such as security policy management, cryptography, data compression, and high-throughput DMA. This is Junior Level position . New grad are allowed to apply .

The Person

The ideal candidate is a highly analytical engineer with strong problem-solving skills and attention to detail, capable of independently driving complex technical tasks to completion. They thrive in a collaborative environment, communicate effectively across hardware and firmware teams, and demonstrate a passion for building scalable, high-performance solutions in security-focused SoC environments. A proactive mindset and the ability to influence design and verification strategies are critical for success in this role. If this sounds like a role you are interested in, we welcome you to apply!

Key Responsibilities

Develop and verify embedded firmware for SoC secure boot and microprocessor-driven hardware acceleration services, including cryptography, compression, and DMA
Perform hardware/firmware co-verification using UVM System Verilog, C-DPI, and FPGA-based prototyping platforms
Define and maintain subsystem verification architecture, testbenches, and methodologies for embedded CPU and IP subsystems using AXI/AHB interfaces
Collaborate on subsystem specification and influence hardware and firmware co-design, including developing abstracted performance models and evaluating architecture trade-offs
Develop and execute block- and subsystem-level test plans using UVM randomized and C-DPI directed methodologies
Build and maintain verification infrastructure, including UVCs, system response models, integration scripts, and build/run environments
Drive verification closure, improve coverage metrics, and debug complex hardware/firmware interactions
Interface with SoC integration and DV teams to support IP-level APIs, SoC-level validation, emulation, silicon bring-up, and debug

Preferred Experience

Strong experience in ASIC firmware and hardware design and verification
Proficiency in C, C++, Assembly, Verilog, System Verilog, and scripting languages such as Python, Perl, and Make
Deep expertise in UVM and C-DPI methodologies
Strong understanding of standard bus/interface protocols (AXI, AHB, AMBA)
Experience with firmware development on commercial microprocessors and associated toolchains (compiler, assembler, debugger)
Hands-on experience with ASIC verification tools, including simulation, linting, and power-aware verification

Academic Credentials

Bachelor’s degree in electrical or computer engineering required; master’s or PhD preferred

LOCATION: Markham, Ottawa

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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More about this job

Responsibilities

Develop and verify embedded firmware and perform hardware/firmware co-verification for secure boot, embedded processors, and hardware acceleration services such as cryptography, compression, and DMA. Build verification architectures and infrastructure, execute block- and subsystem-level testing, drive coverage and debug, and collaborate with design, integration, validation, emulation, and silicon bring-up teams.

Requirements

A bachelor’s degree in electrical or computer engineering is required; a master’s degree or PhD is preferred. The posting seeks experience with ASIC design and verification, UVM and C-DPI, C/C++/Assembly and hardware description languages, AXI/AHB/AMBA protocols, processor firmware toolchains, and ASIC verification tools; new graduates may apply.

Skills

ASIC Verification
Embedded Firmware Development
Hardware/Firmware Co-Verification
UVM
SystemVerilog
C-DPI
C
C++
Assembly
Verilog
Python
Perl
Make
AXI
AHB
FPGA Prototyping

Visa sponsorship

Not detected in the job text

Keywords

ASIC Verification
Embedded Firmware
Hardware/Firmware Co-Verification
Security IP
System-on-Chip (SoC)
Secure Boot
Microprocessors
Hardware Acceleration
Cryptography
Data Compression
DMA
UVM
SystemVerilog
C-DPI
FPGA Prototyping
AXI
AHB
AMBA
C
C++
Assembly
Verilog
Python
Perl
Make
Verification Testbenches
Randomized Testing
Performance Modeling
Simulation
Linting

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