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Added 6 mins ago
MC
Senior QA Engineer III – Automation | Banking | API | Kafka | ETL (35729)
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- Full-time
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AMD

Sr. Manager - RTL Design Manager

Markham, ON, Canada

$167,280 to $250,920 USD / year · Full-time

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Job details

Pay: $167,280 to $250,920 USD / year
Job type: Full-time
Apply by: Nov 8, 2026
Posting language: English
Posted: Oct 9, 2026

Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

The Role

We are seeking a highly motivated Silicon RTL Design Manager to join the Security IP (SECIP) Design team. The team is responsible for the architecture, design, implementation, and verification of a broad portfolio of embedded microprocessor (MP) subsystems and hardware accelerators that enhance performance, functionality, security, and power efficiency across AMD System-on-Chip (SoC) products spanning client, server, graphics, and gaming platforms.

In this role, you will partner closely with IP architecture teams to define IP and subsystem functional specifications, establish and track key design goals, and drive design optimization initiatives. You will collaborate with RTL design, IP integration, power design and analysis, verification, and validation teams to deliver high-quality solutions that meet performance, power, area, and schedule targets.

You will also work with corporate design methodology teams, SoC organizations, and other IP design teams to develop and adopt both traditional and AI-assisted design methodologies and flows. Your expertise will play a critical role in enabling engineering teams to achieve ambitious design objectives across a diverse set of applications while maintaining the highest standards of quality, efficiency, and scalability. This role combines technical leadership, project execution, and people management responsibilities in a fast-paced and highly collaborative environment.

The Person

We are looking for a highly motivated engineering leader with a proven track record of technical excellence, ownership, execution, and team leadership. The ideal candidate is an innovative and analytical thinker who is passionate about solving complex engineering challenges, driving continuous improvement, and developing scalable solutions.

The successful candidate proactively identifies risks, resolves technical issues, and delivers results in a dynamic environment. They excel at mentoring and developing engineers, fostering collaboration across organizations, and building strong, high-performing teams. Strong communication, interpersonal, and organizational skills, combined with attention to detail and sound engineering judgment, are essential for success in this role.

Key Responsibilities

Define, develop, and maintain RTL-level IP and subsystem functional specifications, and align microarchitecture and design solutions with product requirements in collaboration with SoC, architecture, design, verification, and validation teams.
Establish, track, and drive key design metrics and targets by correlating design intent with implementation results and identifying optimization opportunities.
Lead and coordinate RTL design activities from specification through integration and project delivery.
Collaborate with functional and implementation verification teams to debug and resolve design issues across simulation, formal, emulation, and post-silicon validation environments.
Work with corporate methodology and SoC integration teams to adopt and develop traditional and AI-assisted methodologies for microarchitecture development, RTL design, structural analysis, and design validation.
Drive the closure of RTL quality metrics, including lint, CDC, RDC, synthesis, low-power verification, and other implementation-related checks.
Coordinate resolution of IP integration issues with SoC integration, SoC verification, firmware, and post-silicon validation teams.
Partner with project managers, architects, and technical leads to ensure delivery of IP milestones while meeting schedule, quality, power, performance, and area objectives.
Mentor, coach, and develop engineers while fostering a culture of technical excellence, innovation, collaboration, and accountability.

Preferred Experience

Previous experience managing IP or RTL design engineering teams.
Strong expertise in Verilog/SystemVerilog and scripting-based development environments.
Deep knowledge in one or more areas of RTL microarchitecture, digital design, implementation analysis, and industry-standard design methodologies.
Strong understanding of microprocessor (MP) subsystem architectures, datapath design, and low-power design techniques.
Solid understanding of industry-standard on-chip interconnect and interface protocols, including AMBA, AXI, and AHB.
Experience with ASIC design and verification flows, including RTL simulation, linting, CDC/RDC analysis, synthesis, power-aware design and verification, formal verification, and debug methodologies.
Experience correlating RTL design decisions to implementation metrics such as performance, power, area, timing, and overall design quality.
Demonstrated ability to drive technical solutions and collaborate effectively across architecture, design, verification, implementation, methodology, and SoC organizations.
Proven ability to mentor and develop engineers at various career levels while positively influencing team culture and engagement.
Experience leading complex cross-functional projects from concept through silicon bring-up is a strong asset.

Academic Credentials

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.
Master's degree or Ph.D. preferred.

LOCATION: MARKHAM, ON ( Consider Austin, TX)

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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More about this job

Responsibilities

Lead RTL design for security IP and embedded microprocessor subsystems, from functional specifications through integration and delivery, while driving design quality and power, performance, area, and schedule targets. Coordinate cross-functional design, verification, methodology, and SoC integration work, resolve technical issues, and mentor and develop engineers.

Requirements

The role calls for substantial experience leading RTL or IP design teams, strong Verilog/SystemVerilog and ASIC design-flow expertise, and deep knowledge of microarchitecture, digital design, low-power techniques, and on-chip protocols such as AMBA, AXI, and AHB. A bachelor's degree in a relevant engineering or computer science discipline is required in the posting, with a master's degree or Ph.D. preferred; experience leading complex projects through silicon bring-up is an asset.

Skills

RTL Design
Verilog
SystemVerilog
Microarchitecture
Digital Design
ASIC Design
IP Subsystem Architecture
AMBA
AXI
AHB
Low-Power Design
Formal Verification
Linting
CDC/RDC Analysis
Synthesis
Engineering Team Leadership

Visa sponsorship

Not detected in the job text

Keywords

Security IP
RTL Design
Verilog
SystemVerilog
ASIC Design
Microarchitecture
Embedded Microprocessor Subsystems
Hardware Accelerators
System-on-Chip
AMBA
AXI
AHB
Low-Power Design
RTL Simulation
Lint
CDC Analysis
RDC Analysis
Synthesis
Power-Aware Verification
Formal Verification
Emulation
Post-Silicon Validation
Design Methodologies
AI-Assisted Design
Power, Performance, and Area
IP Integration
Silicon Bring-Up
Cross-Functional Project Leadership
Engineering Team Management

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