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AMD

STA/Constraints Engineer

Vancouver, BC, Canada

Pay: $128,000 to $192,000 USD / year
Job type: Full-time
Apply by: Oct 30, 2026
Posting language: English
Posted: Sep 30, 2026

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Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

The Role

The STA/Constraints Engineer is responsible for developing FullChip constraints and timing closure. Person will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers.

KEY RESPONSIBILITIES: 

Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective.
Work closely with the SOC Architecture team for SOC clocks & STA for statistical timing target goals.
Understanding clock design requirements and making sure they are correctly set up in SDC.
Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects.
Understand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.
Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology.
Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.
Work on SDC development, STA (Static Timing) analysis, shift left of timing closure, CDC (Clock Domain Crossing).

PREFERRED EXPERIENCE: 

Industry experience in STA, constraints and timing signoff.
Expert user of industry-standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired).
Good experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.
Excellent presentation and inter-communication skills.
Experience with Verilog RTL design/implementation and has experience of large digital ASIC project.
Experience with physical design is a plus.
Has Synthesis or physical implement experience.
Experience with lower power design methodology.
Good English skills on talking, presentation and writing documents.
Good communication and strong sense of responsibility, task scheduling, and time management.

ACADEMIC CREDENTIALS: 

Bachelor/Master’s degree in Micro Electronics/ Integrated Circuit Science, or related field preferred.

LOCATION: Vancouver, BC

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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More about this job

Responsibilities

Own end-to-end timing constraints and signoff for SoC and subsystem designs, including clock setup, static timing analysis, timing closure, and CDC/lint activities. Collaborate with architecture, physical design, timing, synthesis, CAD, and EDA teams to meet project milestones, improve timing methodologies, and guide design engineers.

Requirements

Candidates should have industry experience in static timing analysis, constraints, and timing signoff, with expertise in Synopsys PrimeTime and GCA; ICC2 or Fusion Compiler experience is desired. The role also calls for scripting skills in Perl, Tcl, Shell, or Python, Verilog RTL experience, familiarity with large digital ASIC projects and low-power methodology, strong communication skills, and a preferred bachelor’s or master’s degree in microelectronics, integrated circuit science, or a related field.

Skills

Static Timing Analysis
Timing Constraints
Timing Signoff
Timing Closure
System-on-Chip Integration
SDC Development
Clock Design
Clock Domain Crossing
CDC and Lint
Low-Power Design
Netlist Quality Checks
PrimeTime
GCA
ICC2
Fusion Compiler
Perl, Tcl, Shell, and Python Scripting

Visa sponsorship

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Keywords

Static Timing Analysis
STA
SDC
Timing Constraints
Timing Signoff
Timing Closure
Full-Chip Constraints
SoC Integration
Subsystem Integration
Clock Design
Statistical Timing
LVF
SSTA
Timing Variations
Clock Domain Crossing
CDC
Lint
Low-Power Design
Netlist Quality
Synopsys PrimeTime
GCA
ICC2
Fusion Compiler
Perl
Tcl
Shell
Python
Verilog RTL
Physical Design
Synthesis

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