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Summer 2027 Long Term ASIC Verification Engineering Intern/ Co-Op

  • Ottawa, ON, Canada
  • Kanata, ON, Canada

$67,000 USD / year · Full-time

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Job details

Pay
$67,000 USD / year
Job type
Full-time
Posting language
English
Posted

Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

As an AMD intern, you’ll be placed at the epicenter of the AI ecosystem, working alongside experts and industry pioneers. You’ll do important work, learn new skills, expand your network, and gain real-world experience on projects that impact millions of end-users worldwide. Whether you’re an undergrad or a PhD student, your contributions matter - and your experience here will be a launchpad for what comes next.

Job Details

  • Location: Ottawa, ON, Canada
  • Onsite/Hybrid: This role requires the student to work full time in a hybrid or onsite work structure throughout the duration of the co-op/intern term.
  • Duration:
  • 12 Months: May 03, 2027 to April 21, 2028
  • 16 Months: May 03, 2027 to August 18, 2028


What You Will Be Doing

You will join our team of experts developing ASIC and Adaptive SoC intellectual property (IP) for the next generation communication networks and data centers. You’ll work with a highly motivated team of engineers developing advanced verification environments for best-in-class configurable silicon targeted for wired communication applications such as AMD’s MI Series Accelerators and Versal SOCs.

  • Contribute to the development of advanced Systemverilog-UVM based verification environments and IP components
  • Write tests, sequences, and testbench components in SystemVerilog and UVM to achieve verification of the design
  • Learn to employ a Coverage-Driven Verification methodology with Constrained Random Stimulus
  • Review and contribute to verification plans and design specifications
  • Contribute to process improvements via automation of tasks and exploring and evaluating new tools and methodologies
  • Investigate and root cause issues found during the IP development stage


Who We Are Looking For

  • 3rd/4th year Computer Engineering or Computer Science students with:
  • Understanding of digital design principles
  • Understanding of Object Oriented Coding practices
  • Experience with AI tools such as Claude Code
  • Experience with Systemverilog, C or C++ programming languages
  • Experience with Python, Perl or other scripting languages is an asset


Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.
More about this job

Responsibilities

Develop advanced Systemverilog-UVM based verification environments and IP components for next-generation communication networks and data centers. Write tests, sequences, and testbench components while investigating and root-causing issues during IP development.

Requirements

Seeking 3rd or 4th year Computer Engineering or Computer Science students with a strong understanding of digital design and object-oriented coding. Proficiency in Systemverilog, C/C++, and experience with AI tools like Claude Code is required.

Skills

  • Systemverilog
  • Uvm
  • C
  • C++
  • Python
  • Perl
  • Digital Design
  • Object Oriented Coding
  • Claude Code
  • Asic Verification
  • Coverage-Driven Verification
  • Constrained Random Stimulus

Visa sponsorship

Not detected in the job text

Categories

  • Engineering
  • Technology
  • Software
  • Manufacturing
  • Science & Research

Keywords

  • Asic
  • Adaptive Soc
  • Systemverilog
  • Uvm
  • Digital Design
  • C
  • C++
  • Python
  • Perl
  • Claude Code
  • Coverage-Driven Verification
  • Constrained Random Stimulus
  • Intellectual Property
  • Semiconductor Manufacturing
  • Wired Communication
  • MI Series Accelerators
  • Versal Socs
  • Verification Plans
  • Automation
  • Root Cause Analysis

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