Full-time jobs in Canada

Explore full-time jobs across Canada. Choose a location and read the full job details.

293,517 listings · 42,510 employers Counted Oct 25, 2026. How we count

About these jobs

Employers hiring include Walmart Canada (6,762 listings), Walmart (2,281 listings), Loblaw Companies Limited (2,272 listings).

Common roles: Cook, Project manager, Sales representative.

56,233 of these listings include employer-provided pay. Open a job to see its currency and pay period.

Advertised starting pay
Pay period	Median starting pay	Listings
CAD / hour	24.00	34,217
CAD / year	80,000.00	18,420
USD / year	98,100.00	1,317
USD / hour	20.00	530
CAD / month	4,981.00	464
CAD / week	1,445.00	45
CAD / day	367.50	32
GBP / year	40,000.00	13
USD / month	4,000.00	13
USD / week	1,635.30	11
EUR / year	72,500.00	10

Employer-listed minimums from at least 10 listings per currency and pay period. These are advertised starting amounts, not employee salaries. Jobs without a minimum and unusual amounts are excluded.

Workplace classifications: 2% remote, 16% hybrid, 82% on-site, 0% not specified. Hybrid and on-site classifications may be inferred from descriptions. Check the original ad.

Based on the dated count above. Listings can change. How we count

Full-time jobs in Canada

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Astera Labs

Physical Design Engineering Director

Toronto, ON, Canada

Base salary range is CAD 200,000 to CAD 250,000 depending on experience, level, and business need.

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Applications open in a new tab.

Job details

Pay: Base salary range is CAD 200,000 to CAD 250,000 depending on experience, level, and business need.
Posting language: English
Posted: Oct 23, 2026

Original job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is seeking a Physical Design Engineering Director to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions deployed across the world's largest AI clusters and hyperscale data centers.

As an Physical Design Engineering Director, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.

Basic Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.
15+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
5+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
Strong scripting ability in Tcl, Python, and/or Perl.
Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience

Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
Experience with Cadence and/or Synopsys physical design tools/flows.

Preferred Experience/Nice to Have

Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
Track record of building and scaling physical design teams through multiple tapeouts.
Knowledge of agentic AI solutions for EDA automation.

Base salary range is CAD 200,000 to CAD 250,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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More about this job

Responsibilities

Lead a team of physical design engineers to drive the implementation of connectivity ASICs from RTL to GDSII. Collaborate with cross-functional teams to ensure design convergence and establish best practices for high-speed serial connectivity products.

Requirements

Requires a bachelor's degree in Electrical or Computer Engineering and over 15 years of experience in physical design implementation at advanced nodes. Candidates must possess strong leadership skills and hands-on expertise in industry-standard EDA tools and scripting languages.

Skills

Physical design
RTL to GDSII
Floorplanning
Place-and-route
Timing closure
Cadence Innovus
Synopsys Fusion Compiler
Tcl
Python
Perl
SerDes
ASIC design
Synthesis
CTS
EM-IR
Equivalence checking

Benefits

Discretionary bonus
Incentives

Visa sponsorship

Not detected in the job text

Keywords

Physical Design
ASIC
Connectivity
AI Infrastructure
CXL
Ethernet
NVLink
PCIe
UALink
COSMOS
RTL
GDSII
Floorplanning
Place-and-route
Timing closure
SerDes
TSMC
Synthesis
CTS
Extraction
EM-IR
DRC
LVS
Cadence Innovus
Synopsys Fusion Compiler
Tcl
Python
Perl
Tapeout
EDA

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