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Added 13 mins ago
MM
Senior Information Management/BIM Manager
Mott MacDonald
Toronto, ON
- Full-time
Work with project managers, engineering leads, BIM/CAD leads, GIS specialists, document control, and Information Management resources to define project-specific digital delivery…
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- Full-time
Lead Engineering for One of Canada's Most Significant Nuclear Projects
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Senior Director, Software Engineering
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- Full-time
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QF
Senior Manager, Operations Transformation
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Toronto, ON
- Full-time
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Added 13 mins ago
AL
Principal DFT Engineer
Astera Labs
Toronto, ON
- Full-time
You will own day-to-day DFT work while partnering with design, verification, physical design, packaging, product engineering, and manufacturing teams. The focus is advanced multi-die…
Added 13 mins ago
QF
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…the team's current needs. The Senior Software Engineer sets engineering standards, mentors developers, partners cross-functionally to ensure scalable and resilient architectures, and owns…
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Added 43 mins ago
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- $95,500 to $140,000 CAD / year
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Senior Project Engineer
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…the team's current needs. The Senior Software Engineer sets engineering standards, mentors developers, partners cross-functionally to ensure scalable and resilient architectures, and owns…
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Mechanical Co-op (Winter 2027)
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Astera Labs

Principal DFT Engineer

Toronto, ON, Canada

Salary range is $165,000 CAD to $210,000 CAD depending on experience, level, and business need. · Full-time

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Job details

Pay: Salary range is $165,000 CAD to $210,000 CAD depending on experience, level, and business need.
Job type: Full-time
Apply by: Nov 25, 2026
Experience: Minimum 8 years of relevant DFT or semiconductor design-and-test experience.
Posting language: English
Posted: Oct 26, 2026

Original job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is seeking a hands-on Principal DFT Engineer to drive DFT architecture and execution for its signal-conditioning products that enable high-speed connectivity in rack-scale AI infrastructure. This is an individual-contributor role focused on technical ownership and delivery.

The role can expand into a people-management path for the right candidate. We are advertising at the Principal individual-contributor level and remain open to discussing a management track where it is a strong fit.

You will own day-to-day DFT work while partnering with design, verification, physical design, packaging, product engineering, and manufacturing teams. The focus is advanced multi-die designs, with emphasis on test coverage, diagnostics, yield, and production readiness for high-speed PCIe and Ethernet products. You will diagnose complex DFT integration and tool-related issues, reason through unfamiliar problems, and help the Toronto team build capability for future multi-die programs.

Key Responsibilities

Define and drive DFT plans for signal-conditioning products supporting high-speed connectivity and advanced multi-die packaging.
Develop test-access, coverage, observability, and diagnostic strategies for die-to-die interfaces, interposers, and package-level integration.
Lead implementation and verification of scan, ATPG, compression, memory BIST, boundary scan, and related DFT features while balancing area, timing, routing, and manufacturability.
Work with Design, STA and Physical Design teams to accurately craft constraints, placement and design structures needed to implement DFT
Set coverage targets, review ATPG results and pattern quality, and influence test-time and production economics.
Support tape-out, wafer sort, packaged-device test, silicon bring-up, characterization, and production ramp.
Collaborate with product, manufacturing, assembly, and test teams on yield learning, failure analysis, and root-cause resolution.
Build pre-bond, post-bond, and package-level test approaches that enable known-good-die screening.
Diagnose DFT integration and tool-related failures and resolve issues cross-functionally.
Mentor engineers and contribute to building DFT capabilities in the team.
Partner with OSATs, ATE vendors, packaging partners, and internal stakeholders; communicate risks and trade-offs clearly.

Required Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
Minimum 8 years of relevant DFT or semiconductor design-and-test experience.
Demonstrated expertise in boundary scan, memory BIST (MBIST), and automatic test pattern generation (ATPG).
Hands-on experience with DFT/EDA tools for test insertion, pattern generation, verification, or diagnostics.
Solid understanding of the ASIC design flow, from RTL through GDS and DFT signoff.
Working knowledge of 2.5D/3D packaging techniques, backside bus implications for test and diagnosis, and DFT methodologies for 3D designs.
Strong analytical and problem-solving skills, with the ability to independently troubleshoot unfamiliar DFT integration and tool-related challenges.
Familiarity with high-speed interface or advanced packaging test concepts.

Preferred Qualifications

Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field.
Working knowledge of multi-die or chiplet DFT experience
Experience with advanced packaging technologies and known-good-die strategies.
Knowledge of relevant IEEE and JEDEC standards for multi-die and boundary-scan testing.
Experience with RTL design, static timing analysis (STA), or physical implementation considerations related to DFT.
Experience with high-speed interface testing, including PCIe, Ethernet, or SerDes.
Familiarity with ATE platforms, wafer probe, OSAT engagement, production testing, and yield analysis.

Salary range is $165,000 CAD to $210,000 CAD depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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More about this job

Responsibilities

Own DFT architecture and execution for high-speed signal-conditioning products, including test strategies for multi-die interfaces, package integration, scan, ATPG, compression, MBIST, and boundary scan. Support tape-out through production ramp, resolve integration and yield issues with cross-functional teams and external partners, and mentor engineers while building team capability.

Requirements

Requires a bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, at least 8 years of relevant DFT or semiconductor design-and-test experience, and demonstrated expertise in boundary scan, MBIST, and ATPG. Candidates should have hands-on DFT/EDA tool experience, understand the ASIC flow through DFT signoff, and be able to troubleshoot complex issues; multi-die, advanced packaging, and high-speed interface experience are valued.

Skills

Design for Test (DFT)
Boundary Scan
Memory BIST (MBIST)
Scan Test
Test Compression
DFT Verification
DFT Signoff
Multi-Die and Chiplet Testing
2.5D/3D Packaging
Known-Good-Die Screening
Silicon Bring-Up
Yield Analysis
Failure Analysis
Static Timing Analysis (STA)
High-Speed Interface Testing

Visa sponsorship

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Keywords

Design for Test (DFT)
Memory BIST (MBIST)
Boundary Scan
Scan Test
Test Compression
DFT Architecture
DFT Signoff
ASIC Design Flow
RTL
GDS
Static Timing Analysis (STA)
Physical Design
2.5D/3D Packaging
Multi-Die Design
Chiplets
Die-to-Die Interfaces
Interposers
Known-Good-Die
PCIe
Ethernet
SerDes
ATE
Wafer Probe
OSAT
Silicon Bring-Up
Yield Analysis
Failure Analysis
IEEE Standards
JEDEC Standards

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Jobs in Canada