SoC Verification Engineer

Job Title: SoC Verification Engineer    

About Blumind

Blumind is a deep-tech startup at the forefront of the AI revolution. We are building a new class of semiconductor devices which are ultra-low-power analog AI processors (AMPL™) designed for Physical AI systems. Our technology enables complex AI, from "always-on" keyword spotting to advanced vision and language models, to run on a small fraction of the power of traditional digital chips. We are on a mission to make high-performance, on-device AI ubiquitous, from wearables and smart home devices to automotive and robotics.

Role Overview

We are seeking an experienced SoC Verification Engineer to join our Silicon Engineering team and own the functional verification of our next-generation AI SoCs. Our chips pair digital control, memory, and interface logic with ultra-low-power analog AI compute, so verification at Blumind goes beyond a conventional digital flow: you will build UVM environments, define coverage-driven test plans, and work side by side with analog designers to verify how the digital and analog domains behave together. Collaborating across digital, analog, and AI/ML teams, you will be a critical safeguard for first-pass silicon success, with real ownership and the opportunity to broaden your skills in AI, analog/digital design, and system-level architecture.

Key Responsibilities

●     Verification Planning: Develop and own verification plans from architecture and design specifications, defining features, test scenarios, coverage goals, and sign-off criteria at block, subsystem, and full-chip level.

●     Testbench Development: Architect, build, and maintain reusable UVM-based verification environments in SystemVerilog, including agents, sequences, scoreboards, reference models, and checkers.

●     Coverage & Assertions: Write functional coverage models and SystemVerilog Assertions (SVA), analyze coverage results, and close coverage holes to drive designs to verification sign-off.

●     Mixed-Signal Co-Verification: Partner with analog designers to verify the interaction between digital control logic and analog AI compute blocks, using behavioral and real-number models where appropriate.

●     System-Level Verification: Verify SoC-level use cases and performance, including data flow through AI inference pipelines, integrating C/C++ or SystemC reference models to check end-to-end behavior.

●     Regression & Automation: Build and maintain regression infrastructure using Python (and Perl or Tcl where needed) to automate test execution, failure triage, and coverage reporting.

●     Debug: Debug simulation failures at block and SoC level, isolate root causes across RTL, testbench, and models, and work with designers to drive fixes to closure.

●     Cross-Functional Collaboration: Work closely with architecture, digital design, analog design, AI/ML, and firmware teams to align verification goals, review specifications and RTL, and flag risks early.

●     Post-Silicon Support: Support silicon bring-up and validation by reproducing silicon issues in simulation, correlating pre- and post-silicon results, and feeding lessons learned back into the verification methodology.

●     Technical Leadership: Contribute to verification methodology and best practices, participate in design and verification reviews, and mentor junior engineers.

Required Qualifications

●     Education: BS or MS in Electrical Engineering, Computer Engineering, or a related discipline.

●     Experience: 8+ years of hands-on experience in ASIC or SoC functional verification, including taking designs through to tape-out.

●     Languages & Methodology: Strong proficiency in SystemVerilog and UVM, including constrained-random stimulus, functional coverage, and assertion-based verification.

●     Scripting: Proficiency in Python for regression automation and data analysis; Perl, Tcl, or shell scripting is an asset.

●     Tools: Hands-on experience with industry-standard simulation and debug tools (e.g., Cadence Xcelium, Synopsys VCS, or Siemens Questa, with Verdi or SimVision).

●     SoC Knowledge: Solid understanding of SoC architecture and verification methodologies, including processors, on-chip buses and interconnects (e.g., AMBA AXI/AHB/APB), memories, interrupts, and peripherals.

●     Problem Solving: Strong problem-solving mindset and a methodical approach to isolating root causes in complex designs.

●     Organization Skills: Self-driven and detail-oriented, with rigorous documentation habits.

●     Teamwork: Excellent communication and collaboration skills, and comfort working in fast-paced, cross-disciplinary environments.

Preferred Qualifications

• Experience with SystemC and C/C++ for reference modeling or transaction-level verification.

• Exposure to AI/ML hardware accelerators, neural network data flows, or DSP datapaths.

• Experience with analog/mixed-signal (AMS) co-verification, real-number modeling (SystemVerilog RNM), or Verilog-AMS.

• Familiarity with low-power verification techniques, including UPF-based power-aware simulation.

• Experience with formal verification tools and methodologies.

• Experience with gate-level simulation, emulation, or FPGA prototyping.

• Experience supporting post-silicon validation and correlating silicon results with pre-silicon simulation.

• Prior work in a semiconductor startup or fast-paced silicon development environment.

Location

• On-site in our Greater Toronto Area or Ottawa, Ontario offices. Candidates willing to relocate will also be considered

We thank all applicants for their interest. Only candidates being considered for the role will be contacted.