Digital Design & Verification (RTL + UVM + Microarchitecture)
- Bluewater, ON, Canada
- Zurich, ON, Canada
Full-time
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Job details
- Job type
- Full-time
- Posting language
- English
- Posted
Original job description
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Digital Design & Verification (RTL + UVM + Microarchitecture)
Confidencial
Descripción del Puesto
Job Description: Senior Digital Design & Verification Engineer
We are searching for Senior Digital Engineers with strong RTL and Verification expertise to join a deep-tech compute architecture team. The role involves hybrid responsibilities across microarchitecture, RTL development, DV environments and subsystem integration.
Responsibilities
– Develop RTL for compute subsystems, controllers, datapaths and interfaces
– Contribute to microarchitecture definition and technical reviews
– Build UVM-based verification environments and test plans
– Drive functional coverage, constrained-random testing and debug
– Support FPGA bring-up and silicon validation activities
– Collaborate with physical design, architecture and mixed-signal teams
Requirements
– Strong background in RTL coding (SystemVerilog/Verilog)
– Solid experience with UVM and modern DV methodologies
– Knowledge of SoC integration, buses, protocols (AXI/APB)
– Exposure to FPGA, DFT, CDC/RDC, linting and subsystem verification
– Ability to work across design + verification flows with technical ownership
Ubicación
Zurich
Salario
120.000 €
Digital Design & Verification (RTL + UVM + Microarchitecture)
Confidencial
Descripción del Puesto
Job Description: Senior Digital Design & Verification Engineer
We are searching for Senior Digital Engineers with strong RTL and Verification expertise to join a deep-tech compute architecture team. The role involves hybrid responsibilities across microarchitecture, RTL development, DV environments and subsystem integration.
Responsibilities
– Develop RTL for compute subsystems, controllers, datapaths and interfaces
– Contribute to microarchitecture definition and technical reviews
– Build UVM-based verification environments and test plans
– Drive functional coverage, constrained-random testing and debug
– Support FPGA bring-up and silicon validation activities
– Collaborate with physical design, architecture and mixed-signal teams
Requirements
– Strong background in RTL coding (SystemVerilog/Verilog)
– Solid experience with UVM and modern DV methodologies
– Knowledge of SoC integration, buses, protocols (AXI/APB)
– Exposure to FPGA, DFT, CDC/RDC, linting and subsystem verification
– Ability to work across design + verification flows with technical ownership
Ubicación
Zurich
Salario
120.000 €
More about this job
Responsibilities
The role involves developing RTL for compute subsystems, controllers, datapaths, and interfaces, as well as contributing to microarchitecture definition and technical reviews. Additionally, the engineer will build UVM-based verification environments and test plans, drive functional coverage, and support FPGA bring-up and silicon validation activities.
Requirements
Candidates should have a strong background in RTL coding, particularly in SystemVerilog or Verilog, and solid experience with UVM and modern DV methodologies. Knowledge of SoC integration, buses, protocols, and exposure to FPGA and subsystem verification is also required.
Skills
- RTL Coding
- SystemVerilog
- Verilog
- UVM
- DV Methodologies
- SoC Integration
- AXI
- APB
- FPGA
- DFT
- CDC
- RDC
- Linting
- Subsystem Verification
Visa sponsorship
Not detected in the job text
Categories
- Technology
- Engineering
- Software
- Consulting
Keywords
- Digital Design
- Verification
- RTL
- UVM
- Microarchitecture
- Compute Architecture
- FPGA
- SoC
- Controllers
- Datapaths
- Interfaces
- Functional Coverage
- Constrained-Random Testing
- Debug
- Silicon Validation
- Physical Design
- Mixed-Signal