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Added 1 month ago
A
Information Technology - Senior Manager/Manager, Analytics & AI, Finance, Legal, Risk Technology
Aritzia
Vancouver, BC
- Full-time
SQL and either Python or R, with the ability to guide technical design, analytical methods, quality assurance, and code-review standards
Added 1 month ago
Crypto Engineer (Contract)
Capco
Toronto, ON
Experience with at least one scripting language, such as Python.
Added 1 month ago
BD
Senior I/O Chiplet RTL Design Engineer
BTA Design Services Inc.
Ottawa, ON
- Full-time
The I/O chiplet connects die-to-die interfaces with multi-protocol high-speed I/O, combining UCIe, PCIe, Ethernet, static switching, and an embedded management subsystem. You will…
Added 1 month ago
A
Senior Manager/Manager, Analytics & AI, Finance, Legal, Risk Technology
Aritzia
Vancouver, BC
- Full-time
SQL and either Python or R, with the ability to guide technical design, analytical methods, quality assurance, and code-review standards
Added 1 month ago
S
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- Full-time
Experience in Programing (Python, R, SQL, NoSQL,Spark) with ML tools & Cloud Technology (AWS, Azure, GCP) with Time Series Forecasting
Added 1 month ago
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Senior Software Engineer, Applied AI (Toronto)
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- $188,000 to $242,000 CAD / year
- Full-time
…program offerings, company retreats, and the ability to interact with and learn from leaders in the startup community. We work hard and care about our most prized asset - our…
Added 1 month ago
Software Development Engineer, WW Deals & Promotions
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Added 1 month ago
NE
Junior Business Data Analyst - Winter 2027 Co-op
Nexus Energy Inc.
Toronto, ON
- $20 to $22 CAD / hour
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…improving processes, and developing solutions using MySQL, Python, and automation. As a key project, you will develop an energy market forecasting model using real-world data, gaining…
Added 1 month ago
Intern - Credit Risk, Winter 2027
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Strong technical proficiency in SQL and Python, with demonstrated ability to manipulate, analyze, and interpret large datasets.
Added 1 month ago
EB
Intern - Credit Risk, Winter 2027
EQ Bank
Toronto, ON
- Internship
Strong technical proficiency in SQL and Python, with demonstrated ability to manipulate, analyze, and interpret large datasets.
Added 1 month ago
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Staff Embedded Software Developer
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Added 1 month ago
Lead Consultant, Gen AI
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…Cloud Migration & Modernization - all delivered on Databricks, with deep partnerships across AWS, Azure, and GCP. To date, we've delivered over $2B in business value for Fortune 500…
Added 2 months ago
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Machine Learning Engineer, Associate Director
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Toronto, ON
- Full-time
…decision-making through strong engineering judgment, and partner closely with engineering leaders, product teams, and fellow engineers to deliver innovative AI solutions at scale. This is a…
Added 1 month ago
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Staff Machine Learning Engineer – AI & Agentic Systems
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Advanced Python development with strong production software-engineering practices (testing, CI/CD, Git)
Added 1 month ago
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- Full-time
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Added 1 month ago
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Added 1 month ago
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Software Developer, Pipeline Integration
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Toronto, ON · Montreal, QC · Vancouver, BC · AMER - Canada - Ontario - Toronto - University Ave
- Full-time
We are seeking a Senior Software Developer to join our team at Autodesk Research. This role focuses on advancing computer graphics pipelines specifically tailored for the AI era within our…
Added 1 month ago
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Machine Learning Developer
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- Full-time
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Added 1 month ago
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BTA Design Services Inc.

Senior I/O Chiplet RTL Design Engineer

Ottawa, ON, Canada

Full-time

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Job details

Job type: Full-time
Apply by: Mar 13, 2027
Experience: Extensive hands-on ASIC RTL design experience, 10 years or more, with ownership through successful tape-out
Posting language: English
Posted: Sep 14, 2026

Original job description

About BTA Design Services
Headquartered in Ottawa, BTA Design Services supports the electronic design community across Canada and internationally, specializing in ASIC and FPGA design, verification, and embedded software development. We strengthen our clients' engineering teams and accelerate the delivery of complete, production-ready designs.

We are adaptable, efficient, and built around exceptional technical talent. Our continued growth reflects the trust our clients place in us, and we are currently searching for a Senior I/O Chiplet RTL Design Engineer.

About the Engagement
The I/O chiplet connects die-to-die interfaces with multi-protocol high-speed I/O, combining UCIe, PCIe, Ethernet, static switching, and an embedded management subsystem. You will collaborate with architecture, RTL, verification, firmware, physical design, and IP partners. Client identity and detailed program specifications are shared under confidentiality during interviews.

About the Position
You will translate architectural requirements into synthesizable SystemVerilog and Verilog, owning assigned blocks from specification through front-end sign-off. The role combines custom datapath and control logic with integration of third-party protocol and PHY IP, with close attention to power, performance, area, and physical implementation.

Key Responsibilities

Define block micro-architecture, interface specifications, and measurable latency, throughput, and resource budgets
Develop configurable static-switch fabrics, protocol multiplexers, pipelined datapaths, and boundary rate-adaptation logic
Configure and integrate protocol and PHY IP, including clocking, reset, status, and control interfaces
Implement CSR access, configuration sequencing, interrupts, and management logic alongside the firmware team
Write assertions and resolve lint, clock-domain crossing (CDC), reset-domain crossing (RDC), and connectivity findings
Develop timing constraints, analyze synthesis results, and work with physical design on partitioning, congestion, and timing closure
Implement low-power controls and support power-intent checks, DFT integration, and formal equivalence activities
Debug failures with verification engineers, maintain design documentation, and deliver reviewed RTL and synthesis handoffs

Must-Have Qualifications

Extensive hands-on ASIC RTL design experience, 10 years or more, with ownership through successful tape-out
Strong SystemVerilog and Verilog skills and experience translating specifications into clear, maintainable RTL
Depth in high-bandwidth datapaths, pipelining, multiplexing, and multi-clock design
Practical experience integrating complex IP and working with at least one high-speed interface such as PCIe, Ethernet, or die-to-die interconnect
Strong understanding of CDC/RDC, reset sequencing, assertions, and static design checks
Hands-on synthesis, timing constraints, and timing-report analysis; ability to resolve issues with physical design
Scripting skills in Python, Tcl, or similar languages to automate design flows
Ability to own technical decisions, lead design reviews, and communicate risks and progress clearly

Nice-to-Have

UCIe or other chiplet interconnect experience, including protocol-to-PHY integration and advanced packaging constraints
PCIe Gen6/Gen7, 200G Ethernet, or 224G PAM4 SerDes integration experience
Advanced-node ASIC delivery, low-power design with UPF, or physically aware RTL partitioning
Embedded RISC-V subsystems, AXI/APB, secure boot, sideband management, or FPGA prototyping experience

Work Arrangement
Ottawa, Canada, is preferred. Hybrid arrangements may be considered based on the candidate and project needs. Clear written communication, independent execution, and collaboration with distributed engineering teams are essential.

Compensation
Compensation will reflect individual experience, technical capability, and the responsibilities of the role. The package will be discussed during the recruitment process.

Why Work With Us
Join an experienced team working on the connectivity challenges behind advanced AI and computing systems. You will have direct technical ownership, close access to architects and implementation specialists, and the opportunity to shape reusable engineering methods for future chiplet programs. We value sound engineering judgment, collaboration, and a sustainable balance between demanding work and life outside it.

Only candidates selected for an interview will be contacted.
DISCLAIMER
BTA Design Services is an equal opportunity employer. We welcome applications from candidates of all backgrounds and are committed to an inclusive, accessible recruitment process. Accommodations are available on request at any stage of hiring.
This posting is for recruitment purposes only and does not constitute an offer of employment or a contract. Role scope, requirements, and compensation are subject to change. All applications are handled in confidence.

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More about this job

Responsibilities

Translate architectural requirements into synthesizable SystemVerilog and Verilog for I/O chiplets, owning blocks from specification to front-end sign-off. Responsibilities include defining micro-architecture, integrating third-party IP, and collaborating with physical design for timing closure.

Requirements

Requires 10+ years of ASIC RTL design experience with a proven track record of successful tape-outs. Candidates must be proficient in high-bandwidth datapaths, high-speed interfaces, and static design checks like CDC/RDC.

Skills

SystemVerilog
Verilog
ASIC RTL Design
PCIe
Ethernet
UCIe
CDC/RDC
Synthesis
Timing Constraints
Python
Tcl
Low-power Design
DFT Integration
Formal Equivalence
Pipelining
Multi-clock Design

Visa sponsorship

Not detected in the job text

Keywords

ASIC
FPGA
RTL
Chiplet
UCIe
PCIe Gen6
PCIe Gen7
200G Ethernet
224G PAM4 SerDes
SystemVerilog
Verilog
CDC
RDC
UPF
RISC-V
AXI
APB
Synthesis
Timing Closure
Python
Tcl
Die-to-Die Interconnect
Low-power Design
DFT
Formal Equivalence
Static Switching
PHY IP
CSR
Pipelining
Micro-architecture

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