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Added 1 month ago
Machine Learning Engineer, Associate Director
Fitch Group
Toronto, ON
…we're establishing Toronto as our AI innovation center. As a Lead ML Engineer, you'll be a technical champion driving this transformation - building breakthrough ML systems that others will…
Added 1 month ago
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Information Technology - Senior Manager/Manager, Analytics & AI, Finance, Legal, Risk Technology
Aritzia
Vancouver, BC
- Full-time
Lead the design and delivery of governed semantic models, dashboards, self-service reporting, predictive analytics, scenario models, and exception-based insights that establish trusted…
Added 1 month ago
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System Integration Technical Lead
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Surrey, BC
- Full-time
The Systems Integration Technical Lead is responsible for ensuring Delta Controls products work effectively together as an integrated system and meet the needs of their intended…
Added 1 month ago
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Senior Consultant, Air Quality
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Vancouver, BC
- Full-time
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Added 1 month ago
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Senior Air Quality Engineer
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Air Quality Technician
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Lead and execute ambient air quality, meteorological, and environmental monitoring field programs across urban, industrial, and remote environments.
Added 1 month ago
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Senior I/O Chiplet RTL Design Engineer
BTA Design Services Inc.
Ottawa, ON
- Full-time
Scripting skills in Python, Tcl, or similar languages to automate design flows
Added 1 month ago
A
Senior Manager/Manager, Analytics & AI, Finance, Legal, Risk Technology
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Added 1 month ago
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Lead Data Scientist
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- Full-time
Summary: The role is expected to serve as the primary client-facing data science lead to design, build, and scale advanced AI and machine learning solutions for enterprise clients. This…
Added 1 month ago
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Senior BI ETL Developer
KTek Resourcing
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- Contract
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Senior Java Software Engineer
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Added 1 month ago
Lead Consultant, Gen AI
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Kubernetes Systems Administrator – L3
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Vancouver, BC
Proficiency in scripting languages such as Python, Ruby, Perl, and/or Bash
Added 1 month ago
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Machine Learning Engineer, Associate Director
Fitch Group, Inc.
Toronto, ON
- Full-time
…we're establishing Toronto as our AI innovation center. As a Lead ML Engineer, you'll be a technical champion driving this transformation - building breakthrough ML systems that others will…
Added 1 month ago
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- Full-time
Design, build, test, and optimize scalable data models and ETL/ELT pipelines within Databricks using Python, PySpark, SQL, notebooks, workflows, and orchestration frameworks to support…
Added 2 months ago
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Founding Engineering Lead
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- Full-time
We're looking for a Founding Engineering Lead for the technical evolution of Docufy AI.
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Principal Lead AI Developer
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A career as a Lead AI Developer within the Commercial and 1859 team at National Bank means acting as a specialist in the development of advanced technology solutions. In this role, you will…
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Kubernetes Systems Administrator – L3
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Vancouver, BC
- Full-time
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Managing Director, Data Product Lead - COO Group
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The Data Product Lead will define strategy, lead execution, partner across business and technology, and deliver measurable business value through modern data capabilities.
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Managing Director, Data Product Lead - COO Group
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Added 1 month ago
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Senior RPA Automation Engineer
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…the organization. As a Senior Automation Engineer, you will lead the full lifecycle of automation initiatives - from process discovery and solution design to development, deployment,…
Added 1 month ago
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Data Center Silicon Hardware Engineering Intern - Winter 2027
Marvell Technology
Toronto, ON · Ottawa, ON · CA-ON - Ottawa
- Full-time
…beyond fleeting trends, Marvell is a place to thrive, learn, and…
Added 1 month ago
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Staff Engineer - Inference /AI
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Vancouver, BC
- $171,000 to $257,000 CAD / year
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You will report to a seasoned Technical Lead/Manager who will provide mentorship and guidance as you navigate through your responsibilities. The work setup at Nutanix AI is a hybrid model,…
Added 1 month ago
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Consultant, IT Quality Assurance
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- Full-time
…highest quality. As a Senior Test Coordinator, you’ll be a team lead on CIBC’s Technology team, assigning and overseeing the execution of test cases and providing coaching to your team…
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Proficiency in Python for data processing, automation, and integration activities.

BTA Design Services Inc.

Senior I/O Chiplet RTL Design Engineer

Ottawa, ON, Canada

Full-time

Apply About employer

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Job details

Job type: Full-time
Apply by: Mar 13, 2027
Experience: Extensive hands-on ASIC RTL design experience, 10 years or more, with ownership through successful tape-out
Posting language: English
Posted: Sep 14, 2026

Original job description

About BTA Design Services
Headquartered in Ottawa, BTA Design Services supports the electronic design community across Canada and internationally, specializing in ASIC and FPGA design, verification, and embedded software development. We strengthen our clients' engineering teams and accelerate the delivery of complete, production-ready designs.

We are adaptable, efficient, and built around exceptional technical talent. Our continued growth reflects the trust our clients place in us, and we are currently searching for a Senior I/O Chiplet RTL Design Engineer.

About the Engagement
The I/O chiplet connects die-to-die interfaces with multi-protocol high-speed I/O, combining UCIe, PCIe, Ethernet, static switching, and an embedded management subsystem. You will collaborate with architecture, RTL, verification, firmware, physical design, and IP partners. Client identity and detailed program specifications are shared under confidentiality during interviews.

About the Position
You will translate architectural requirements into synthesizable SystemVerilog and Verilog, owning assigned blocks from specification through front-end sign-off. The role combines custom datapath and control logic with integration of third-party protocol and PHY IP, with close attention to power, performance, area, and physical implementation.

Key Responsibilities

Define block micro-architecture, interface specifications, and measurable latency, throughput, and resource budgets
Develop configurable static-switch fabrics, protocol multiplexers, pipelined datapaths, and boundary rate-adaptation logic
Configure and integrate protocol and PHY IP, including clocking, reset, status, and control interfaces
Implement CSR access, configuration sequencing, interrupts, and management logic alongside the firmware team
Write assertions and resolve lint, clock-domain crossing (CDC), reset-domain crossing (RDC), and connectivity findings
Develop timing constraints, analyze synthesis results, and work with physical design on partitioning, congestion, and timing closure
Implement low-power controls and support power-intent checks, DFT integration, and formal equivalence activities
Debug failures with verification engineers, maintain design documentation, and deliver reviewed RTL and synthesis handoffs

Must-Have Qualifications

Extensive hands-on ASIC RTL design experience, 10 years or more, with ownership through successful tape-out
Strong SystemVerilog and Verilog skills and experience translating specifications into clear, maintainable RTL
Depth in high-bandwidth datapaths, pipelining, multiplexing, and multi-clock design
Practical experience integrating complex IP and working with at least one high-speed interface such as PCIe, Ethernet, or die-to-die interconnect
Strong understanding of CDC/RDC, reset sequencing, assertions, and static design checks
Hands-on synthesis, timing constraints, and timing-report analysis; ability to resolve issues with physical design
Scripting skills in Python, Tcl, or similar languages to automate design flows
Ability to own technical decisions, lead design reviews, and communicate risks and progress clearly

Nice-to-Have

UCIe or other chiplet interconnect experience, including protocol-to-PHY integration and advanced packaging constraints
PCIe Gen6/Gen7, 200G Ethernet, or 224G PAM4 SerDes integration experience
Advanced-node ASIC delivery, low-power design with UPF, or physically aware RTL partitioning
Embedded RISC-V subsystems, AXI/APB, secure boot, sideband management, or FPGA prototyping experience

Work Arrangement
Ottawa, Canada, is preferred. Hybrid arrangements may be considered based on the candidate and project needs. Clear written communication, independent execution, and collaboration with distributed engineering teams are essential.

Compensation
Compensation will reflect individual experience, technical capability, and the responsibilities of the role. The package will be discussed during the recruitment process.

Why Work With Us
Join an experienced team working on the connectivity challenges behind advanced AI and computing systems. You will have direct technical ownership, close access to architects and implementation specialists, and the opportunity to shape reusable engineering methods for future chiplet programs. We value sound engineering judgment, collaboration, and a sustainable balance between demanding work and life outside it.

Only candidates selected for an interview will be contacted.
DISCLAIMER
BTA Design Services is an equal opportunity employer. We welcome applications from candidates of all backgrounds and are committed to an inclusive, accessible recruitment process. Accommodations are available on request at any stage of hiring.
This posting is for recruitment purposes only and does not constitute an offer of employment or a contract. Role scope, requirements, and compensation are subject to change. All applications are handled in confidence.

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More about this job

Responsibilities

Translate architectural requirements into synthesizable SystemVerilog and Verilog for I/O chiplets, owning blocks from specification to front-end sign-off. Responsibilities include defining micro-architecture, integrating third-party IP, and collaborating with physical design for timing closure.

Requirements

Requires 10+ years of ASIC RTL design experience with a proven track record of successful tape-outs. Candidates must be proficient in high-bandwidth datapaths, high-speed interfaces, and static design checks like CDC/RDC.

Skills

SystemVerilog
Verilog
ASIC RTL Design
PCIe
Ethernet
UCIe
CDC/RDC
Synthesis
Timing Constraints
Python
Tcl
Low-power Design
DFT Integration
Formal Equivalence
Pipelining
Multi-clock Design

Visa sponsorship

Not detected in the job text

Keywords

ASIC
FPGA
RTL
Chiplet
UCIe
PCIe Gen6
PCIe Gen7
200G Ethernet
224G PAM4 SerDes
SystemVerilog
Verilog
CDC
RDC
UPF
RISC-V
AXI
APB
Synthesis
Timing Closure
Python
Tcl
Die-to-Die Interconnect
Low-power Design
DFT
Formal Equivalence
Static Switching
PHY IP
CSR
Pipelining
Micro-architecture

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