Jobs in Canada

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Added 1 hour ago
I
Intermediate/Senior Digital IC Design Engineer
INNOSILICON
Ottawa, ON
- Full-time
Innosilicon is seeking to hire an Intermediate/Senior Digital IC Design Engineer to join our Inter-connectivity Memory Business Unit. The successful candidate will work with our experienced…
Added 11 days ago
Senior FPGA Research Engineer
Barco
Vancouver, BC
Barco's Vancouver team is developing FPGA-based sensing and edge AI capabilities for industrial applications. We are looking for a hands-on senior FPGA engineer to lead the sensor…
Added 16 days ago
AM
RTL Design Engineer
Advanced Micro Devices, Inc
Markham, ON
- Full-time
We are seeking a highly motivated RTL IP Design Engineer to join AMD's Security IP (SECIP) Design team. The team is responsible for the architecture, design, and verification of a broad…
Added 17 days ago
KC
Senior Flight Software Designer (6+ month Contract)
Kepler Communications Inc.
Canada
- Contract
…building the Kepler spacecraft. You will be responsible for the design and implementation of FPGA code either with a focus on DSP algorithms to modulate and demodulate signals on board our…
Added 18 days ago
V
Senior Firmware & FPGA Engineer, SST Control
Verdyn
Oakville, ON
- $110,000 to $160,000 CAD / year
- Full-time
We're looking for a Senior Firmware & FPGA Engineer to own firmware development of our solid state transformer at our Oakville facility. You'll own the real-time control firmware and FPGA…
Added 18 days ago
AM
RTL Design Engineer
Advanced Micro Devices, Inc
Markham, ON
- Full-time
We are seeking a highly motivated RTL IP Design Engineer to join AMD's Security IP (SECIP) Design team. The team is responsible for the architecture, design, and verification of a broad…
Added 25 days ago
Q
FPGA Design & Firmware Engineer, Staff
Qualcomm
Markham, ON
- Full-time
Join the Qualcomm Global CAD team developing advanced FPGA-based emulation and prototyping solutions supporting next-generation IoT, mobile, compute, and data center platforms. We are…
Added 25 days ago
MC
FPGA Design & Validation Engineer – 4G 5G Radio (35952)
Myticas Consulting
Ottawa, ON
- Contract
FPGA Design & Validation Engineer – 4G/5G Radio Units
Added 1 month ago
MC
FPGA Design & Validation Engineer – 4G 5G Radio (35952)
Myticas Consulting
Ottawa, ON
- Contract
FPGA Design & Validation Engineer – 4G/5G Radio Units
Added 1 month ago
AM
RTL Design Engineer
Advanced Micro Devices, Inc
Markham, ON
- Full-time
We are seeking a highly motivated RTL IP Design Engineer to join AMD's Security IP (SECIP) Design team. The team is responsible for the architecture, design, and verification of a broad…
Added 1 month ago
AM
Senior ASIC RTL Design Engineer, AI Networking IP
Advanced Micro Devices, Inc
Ottawa, ON
- Full-time
We are looking for a talented ASIC RTL Design Engineer to join our IP design team developing high-performance networking and communications IP for advanced AMD products. Our intellectual…
Added 1 month ago
A
Senior ASIC RTL Design Engineer, AI Networking IP
AMD
Ottawa, ON · Kanata, ON
- $128,000 to $192,000 CAD / year
- Full-time
We are looking for a talented ASIC RTL Design Engineer to join our IP design team developing high-performance networking and communications IP for advanced AMD products. Our intellectual…
Added 1 month ago
PG
Principal Hardware Engineer
PRI Global
Ottawa, ON
- Contract
Optimize FPGA resource utilization and ensure timing closure.
Added 1 month ago
SN
FPGA Design Engineer
Stefanini North America and APAC
Ottawa, ON · Kanata, ON
- Contract
IMP: Digital Signal Processing (DSP) is a must have skill for the role
Added 1 month ago
S
Senior IC Digital Design Engineer
StarIC
Toronto, ON
- Full-time
Responsible for all phases of the design cycle (specification, modeling, RTL, verification, synthesis, timing closure, vector generation and simulation, lab testing, layout support and…
Added 1 month ago
UT
Senior ASIC RTL Design Engineer
USA Tech Recruit
Ottawa, ON
- $150,000 to $200,000 CAD / year
- Full-time
We are looking for a Senior ASIC RTL Design Engineer to join a long-term client engagement focused on an advanced I/O chiplet combining die-to-die connectivity with multi-protocol,…
Added 1 month ago
BD
Senior I/O Chiplet RTL Design Engineer
BTA Design Services Inc.
Ottawa, ON
- Full-time
…our clients place in us, and we are currently searching for a Senior I/O Chiplet RTL Design…
Added 1 month ago
BD
Senior I/O Chiplet RTL Design Engineer
BTA Design Services
Ottawa, ON
- Full-time
…our clients place in us, and we are currently searching for a Senior I/O Chiplet RTL Design…
Added 2 months ago
BD
Senior Physical Design Engineer - P&R
BTA Design Services
Remote, Canada
- Full-time
- Remote
As a Senior Physical Design Engineer, you will own backend implementation from netlist to GDSII on challenging blocks and sub-systems. You will apply advanced flows and techniques on…
Added 3 months ago
R
SMTS Logic Design
Rambus
Montreal, QC
- Other
Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work
Added 4 months ago
CG
Senior/Expert Hardware Design Engineer - FPGA
CS GROUP
Montreal, Quebec
- Full-time
CS Group Canada is seeking a Senior/Expert Hardware Design Engineer with strong experience in video and audio systems to contribute the development and certification of automotive and…
Added 2 months ago
Senior Digital Design Engineer
Astera Labs
Toronto, ON
As a Senior Digital Design Engineer, you will design and integrate high-performance connectivity silicon for the next generation of AI infrastructure. You will contribute across…
Added 3 months ago
MT
Senior Engineer - Design
Microchip Technology Inc.
Burnaby, British Columbia · Canada - Burnaby
- Full-time
Microchip’s Datacenter Solutions (DCS) group is looking for an experienced Design Engineer to join the storage controller team developing the next generation of advanced storage controller…

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BTA Design Services

Senior I/O Chiplet RTL Design Engineer

Ottawa, ON, Canada

Full-time

Apply on btadesignservices.applytojob.com About employer

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Job details

Job type: Full-time
Apply by: Dec 13, 2026
Experience: Extensive hands-on ASIC RTL design experience, 10 years or more, with ownership through successful tape-out.
Posting language: English
Posted: Sep 14, 2026

Original job description

About BTA Design Services
Headquartered in Ottawa, BTA Design Services supports the electronic design community across Canada and internationally, specializing in ASIC and FPGA design, verification, and embedded software development. We strengthen our clients' engineering teams and accelerate the delivery of complete, production ready designs.

We are adaptable, efficient, and built around exceptional technical talent. Our continued growth reflects the trust our clients place in us, and we are currently searching for a Senior I/O Chiplet RTL Design Engineer.

About the Engagement
The I/O chiplet connects die-to-die interfaces with multi-protocol high-speed I/O, combining UCIe, PCIe, Ethernet, static switching, and an embedded management subsystem. You will collaborate with architecture, RTL, verification, firmware, physical design, and IP partners. Client identity and detailed program specifications are shared under confidentiality during interviews.

About the Position
You will translate architectural requirements into synthesizable SystemVerilog and Verilog, owning assigned blocks from specification through front-end sign-off. The role combines custom datapath and control logic with integration of third-party protocol and PHY IP, with close attention to power, performance, area, and physical implementation.

Key Responsibilities

Define block micro-architecture, interface specifications, and measurable latency, throughput, and resource budgets.
Develop configurable static-switch fabrics, protocol multiplexers, pipelined datapaths, and boundary rate-adaptation logic.
Configure and integrate protocol and PHY IP, including clocking, reset, status, and control interfaces.
Implement CSR access, configuration sequencing, interrupts, and management logic alongside the firmware team.
Write assertions and resolve lint, clock-domain crossing (CDC), reset-domain crossing (RDC), and connectivity findings.
Develop timing constraints, analyze synthesis results, and work with physical design on partitioning, congestion, and timing closure.
Implement low-power controls and support power-intent checks, DFT integration, and formal equivalence activities.
Debug failures with verification engineers, maintain design documentation, and deliver reviewed RTL and synthesis handoffs.

Must-Have Qualifications

Extensive hands-on ASIC RTL design experience, 10 years or more, with ownership through successful tape-out.
Strong SystemVerilog and Verilog skills and experience translating specifications into clear, maintainable RTL.
Depth in high-bandwidth datapaths, pipelining, multiplexing, and multi-clock design.
Practical experience integrating complex IP and working with at least one high-speed interface such as PCIe, Ethernet, or die-to-die interconnect.
Strong understanding of CDC/RDC, reset sequencing, assertions, and static design checks.
Hands-on synthesis, timing constraints, and timing-report analysis; ability to resolve issues with physical design.
Scripting skills in Python, Tcl, or similar languages to automate design flows.
Ability to own technical decisions, lead design reviews, and communicate risks and progress clearly.

Nice-to-Have

UCIe or other chiplet interconnect experience, including protocol-to-PHY integration and advanced packaging constraints.
PCIe Gen6/Gen7, 200G Ethernet, or 224G PAM4 SerDes integration experience.
Advanced-node ASIC delivery, low-power design with UPF, or physically aware RTL partitioning.
Embedded RISC-V subsystems, AXI/APB, secure boot, sideband management, or FPGA prototyping experience.

Work Arrangement
Ottawa, Canada, is preferred. Hybrid arrangements may be considered based on the candidate and project needs. Clear written communication, independent execution, and collaboration with distributed engineering teams are essential.

Compensation
Compensation will reflect individual experience, technical capability, and the responsibilities of the role. The package will be discussed during the recruitment process.

Why Work With Us
Join an experienced team working on the connectivity challenges behind advanced AI and computing systems. You will have direct technical ownership, close access to architects and implementation specialists, and the opportunity to shape reusable engineering methods for future chiplet programs. We value sound engineering judgment, collaboration, and a sustainable balance between demanding work and life outside it.

Only candidates selected for an interview will be contacted.
DISCLAIMER
Manitechs Engineering is an equal opportunity employer. We welcome applications from candidates of all backgrounds and are committed to an inclusive, accessible recruitment process. Accommodations are available on request at any stage of hiring.
This posting is for recruitment purposes only and does not constitute an offer of employment or a contract. Role scope, requirements, and compensation are subject to change. All applications are handled in confidence.

Apply on btadesignservices.applytojob.com About employer

More about this job

Responsibilities

You will translate architectural requirements into synthesizable RTL and own assigned blocks from specification through front-end sign-off. The role involves integrating complex IP, developing static-switch fabrics, and collaborating with cross-functional teams to ensure power, performance, and area targets are met.

Requirements

Candidates must have at least 10 years of hands-on ASIC RTL design experience with a proven track record of successful tape-outs. Strong proficiency in SystemVerilog, Verilog, and high-speed interface integration is required, along with the ability to manage timing constraints and synthesis flows.

Skills

RTL Design
SystemVerilog
Verilog
ASIC
Chiplet
PCIe
Ethernet
UCIe
Synthesis
Timing Constraints
CDC
RDC
Python
Tcl
Low-power Design
IP Integration

Visa sponsorship

Not detected in the job text

Keywords

ASIC
RTL Design
SystemVerilog
Verilog
Chiplet
UCIe
PCIe
Ethernet
Synthesis
Timing Closure
CDC
RDC
Python
Tcl
IP Integration
PHY
Datapath
Pipelining
Low-power Design
UPF
DFT
Formal Equivalence
CSR
RISC-V
AXI
APB
FPGA
SerDes
PAM4
Tape-out

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Jobs in Canada