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Added 15 mins ago
A
Process Manager***Gestionairre de processus
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CA - Pharmacy - Plant (EXT)
- Full-time
Lead Manufacturing Execution System (MES) initiatives and support the adoption of digital manufacturing tools that enhance operational visibility and efficiency.
Added 15 mins ago
IG
Process Manager***Gestionairre de processus
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CA - Pharmacy - Plant (EXT)
- Full-time
Lead Manufacturing Execution System (MES) initiatives and support the adoption of digital manufacturing tools that enhance operational visibility and efficiency.
Added 30 mins ago
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Enterprise Network Architect
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- Internship
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Software Architect
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Cadence Design Systems

Lead Digital Verification Engineer

Montreal, QC, Canada

The annual salary range for MOUNT-ROYAL 01 (Montreal)is 89,600.00 - 166,400.00 CAD Annual CAD Annual. · Full-time

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Job details

Pay: The annual salary range for MOUNT-ROYAL 01 (Montreal)is 89,600.00 - 166,400.00 CAD Annual CAD Annual.
Job type: Full-time
Posting language: English · French
Posted: Nov 3, 2026

Original job description

English section of this bilingual listing.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This role is for an existing vacancy.

Job Title: Lead Verification Engineer

Location: Montreal, Ottawa, Toronto

Overview

This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols.

The successful candidate will be a highly motivated self-starter who is able to work independently to complete assigned tasks within required project timelines with high quality.

The candidate will primarily be responsible for the verification of digital RTL and development of re-usable verification components and environments.

It is also expected that the candidate will contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure.

The ideal candidate will have a fundamental understanding of the end-to-end verification flow in order to accurately and efficiently communicate with all members of the technical staff regarding overall project development progress and status.

The most successful candidates will be able to demonstrate excellent command of fundamental logic principles as well as excellent problem solving and communication skills.

The candidate should be able to work as part of a small and focused team of engineers and be able to collaborate successfully as needed with design teams, verification teams, project management, and digital and analog design teams in multiple worldwide geographies.

The Candidate should be willing to work full time in the Montreal, Quebec, Canada office and be willing to travel as required by job function (expectation is 5% travel or less).

Design IP is growing organization within Cadence and our complete IP portfolio can be found here http://ip.cadence.com/ipportfolio/ip-portfolio-overview.

Minimum Experience:

Bachelor of Science in Electrical(EE)/Computer Engineering (CPE) or Computer Science (CSC)
Understanding of verification architecture and methodologies
Understanding of Metric Driven Verification
Understanding of Universal Verification Methodologies
Understanding of the identification, planning and creation of functional coverage and checks
Understanding of System Verilog Assertions (SVAs)
Understanding of digital design flow

Preferred Experience:

Master of Science in EE/CPE/CSC
Experience with SystemVerilog UVM coding language is desired
Experience with scripting languages such as Python, Perl, Ruby, Sed, or Awk is also strongly preferred
Exposure to Standard Protocol knowledge for any of the following areas: PCIe, USB, SATA, Ethernet, Display Port, HDMI
Exposure to Formal Verification Technologies
Exposure to Mixed Signal Design experience
Experience with Cadence tools experience
Exposure to Low Power verification experience using CPF or UPF

Cadence is an equal-opportunity employer committed to hiring a diverse workforce.

Titre: Concepteur en Vérification Numérique

Localisation: Montreal, Ottawa, Toronto

The annual salary range for MOUNT-ROYAL 01 (Montreal)is 89,600.00 - 166,400.00 CAD Annual CAD Annual. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Our benefits programs include: paid vacation and holidays, leave of absence programs, Registered Retirement Savings Plan (RRSP), Tax Free Savings (TFSA) plan for post-tax investment savings, Employee Stock Purchase Plan, group health coverage that includes dental, vision and Emotional Wellbeing Support (EAP) benefits for you and your eligible dependents. Cadence also offers employee and dependent Life insurance, and short-term and long-term disability. In addition, Cadence provides Global Travel Medical coverage, Business Travel Accident Insurance, and a funded Lifestyle Spending Account (LSA).

We’re doing work that matters. Help us solve what others can’t.

Read the full bilingual original

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This role is for an existing vacancy.

Job Title: Lead Verification Engineer

Location: Montreal, Ottawa, Toronto

Overview

This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols.

The successful candidate will be a highly motivated self-starter who is able to work independently to complete assigned tasks within required project timelines with high quality.

The candidate will primarily be responsible for the verification of digital RTL and development of re-usable verification components and environments.

The most successful candidates will be able to demonstrate excellent command of fundamental logic principles as well as excellent problem solving and communication skills.

The Candidate should be willing to work full time in the Montreal, Quebec, Canada office and be willing to travel as required by job function (expectation is 5% travel or less).

Design IP is growing organization within Cadence and our complete IP portfolio can be found here http://ip.cadence.com/ipportfolio/ip-portfolio-overview.

Minimum Experience:

Bachelor of Science in Electrical(EE)/Computer Engineering (CPE) or Computer Science (CSC)
Understanding of verification architecture and methodologies
Understanding of Metric Driven Verification
Understanding of Universal Verification Methodologies
Understanding of the identification, planning and creation of functional coverage and checks
Understanding of System Verilog Assertions (SVAs)
Understanding of digital design flow

Preferred Experience:

Master of Science in EE/CPE/CSC
Experience with SystemVerilog UVM coding language is desired
Experience with scripting languages such as Python, Perl, Ruby, Sed, or Awk is also strongly preferred
Exposure to Standard Protocol knowledge for any of the following areas: PCIe, USB, SATA, Ethernet, Display Port, HDMI
Exposure to Formal Verification Technologies
Exposure to Mixed Signal Design experience
Experience with Cadence tools experience
Exposure to Low Power verification experience using CPF or UPF

Cadence is an equal-opportunity employer committed to hiring a diverse workforce.

Titre: Concepteur en Vérification Numérique

Localisation: Montreal, Ottawa, Toronto

Description :

Cadence Design Systems est à la recherche de candidats d’excellence pour joindre une équipe expérimentée et dynamique d’ingénieurs en charge du développement d’IP au service des standards de l’industrie.

Le candidat sélectionné aura la charge de la vérification de modules numériques RTL et du développement de modules de vérification réutilisables. Le candidat sera aussi amené à contribuer à toutes les phases du processus de vérification : élaboration du plan de vérification, codage des points de couverture, génération de stimuli et analyse de couverture.

Le candidat devra posséder des connaissances de base des méthodes de design et de vérification des composantes numériques.

Le candidat devra être autonome, dynamique et démontrer de très bonnes qualités de communication.

Le groupe de design IP est une équipe multidisciplinaire composée d’ingénieurs provenant de divers sites à travers le monde.

Faisant parti du groupe de vérification, le candidat sera amené à collaborer avec diverses disciplines et phases de la réalisation complète d’IP matériel : design numérique et analogique, design physique, production, etc.

Le groupe de design IP est une organisation grandissante. Le catalogue complet se trouve au site suivant : http://ip.cadence.com/ipportfolio/ip-portfolio-overview.

Expérience minimum:

Baccalauréat en Ingénierie électrique, sciences appliquées ou domaine connexe.
Compréhension des principes de base de la vérification de composantes numériques.
Compréhension de base de la vérification basées sur les métriques (Metric Driven Verification).
Connaissance des Méthodes de Vérification Universelles (UVM).
Connaissance du langage d’assertions SystemVerilog (SVAs).
Compréhension de base du flot de design numérique.
Capable de communiquer en anglais.

Expérience recherchée:

Maîtrise en génie électrique, sciences appliquées ou domaine connexe.
Expérience avec le langage de vérification SystemVerilog UVM.
Expérience avec différents langages de script tel que Python, Perl, Ruby, etc.
Connaissance de base des protocoles de transfert de données tel que PCIe, USB, SATA, Ethernet, Display Port, HDMI.
Connaissance de base des techniques de vérification formelle.
Connaissance de base des composantes mixtes (analogiques/numériques).

Cadence est une employeuse qui souscrit à l’égalité des chances et qui s’engage à embaucher une main-d’oeuvre diversifiée.

We’re doing work that matters. Help us solve what others can’t.

Apply About employer

More about this job

Responsibilities

The candidate will be responsible for the verification of digital RTL and the development of reusable verification components and environments. They will also contribute to flow development, test plan execution, and functional and code coverage closure.

Requirements

The role requires a Bachelor's degree in Electrical, Computer Engineering, or Computer Science, with a strong understanding of verification architecture and methodologies. Candidates should possess excellent command of logic principles and experience with SystemVerilog and UVM.

Skills

Digital verification
RTL
SystemVerilog
UVM
Metric Driven Verification
Functional coverage
Code coverage
SVAs
Python
Perl
PCIe
USB
Ethernet
Formal verification
Mixed signal design
Low power verification

Benefits

Paid vacation and holidays
Leave of absence programs
Tax Free Savings (TFSA) plan
Employee Stock Purchase Plan
Group health coverage
Dental insurance
Vision insurance
Emotional Wellbeing Support (EAP)
Life insurance
Short-term disability
Long-term disability
Global Travel Medical coverage
Business Travel Accident Insurance

Visa sponsorship

Not detected in the job text

Keywords

Digital Verification
RTL
SystemVerilog
UVM
Metric Driven Verification
Functional Coverage
Code Coverage
SVA
Python
Perl
Ruby
PCIe
USB
SATA
Ethernet
Display Port
HDMI
Formal Verification
Mixed Signal Design
Low Power Verification
CPF
UPF
Cadence Tools
Physical IP
Digital Design Flow

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