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Added 1 month ago
Senior Data & AI Consultant
Lantern
Edmonton, AB · Toronto, ON
…scalable solutions that support analytics, machine learning, generative AI, and intelligent…
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Data Architect
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Staff AI Engineer
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- $147,000 to $167,000 CAD / year
- Full-time
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Safe Software is looking for a Staff AI Engineer to design, build, and deploy production-grade AI systems across the organization.
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SDET Contractor
PlayStation Global
Waterloo, ON
We are looking for an experienced Software Development Engineer in Test (SDET) to help ensure the quality, reliability, and resilience of Agentic AI systems and backend services. This role…
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Ingénieur(e) principal(e) en réseaux de puissance / Lead Power System Engineer
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Eaton's Electrical Engineering Services and Systems division is currently seeking a Lead Power System Engineer. This role is based in our Eaton Americas Innovation Center in Brossard,…
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Staff Machine Learning Engineer, SecureAI
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- $168,000 to $231,000 CAD / year
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AI Full Stack Developer
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Sr. Engineer - AI Solutions
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Aurora, ON · Toronto, ON
- $102,500 to $124,700 CAD / year
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…cost factors associated with the technology. The Sr. Research Engineer will plan, execute and coordinate R&D programs for/with internal and external R&D departments, (supplier) companies,…
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Manager, Product Engineering & Development - Full-Stack Builder
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Senior Software Development Engineer, Amazon Customer Service
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…worldwide, and we're seeking a Senior Software Development Engineer to help build the next generation of intelligent solutions. In this role, you'll design and implement agentic systems…
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Hardware Development Engineer
Accuenergy Canada Inc
Toronto, ON
- $50,000 to $70,000 CAD / year
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Ingénieur structure (DTA) / DTA Stress Engineer
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- $100,200 to $125,747 CAD / year
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Interiors Integrator Engineer (Hybrid: Mirabel, Quebec)
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Soutien en service - Ingénieur de conception / In-Service Support - Design Engineer
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Added 1 month ago
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Analog and RF Layout Engineer
Capgemini Engineering
Toronto, ON
- Full-time
Capgemini Engineering is seeking a Senior Analog / RF IC Layout Engineer to join our growing semiconductor engineering team in the Greater Toronto Area. This is an exciting opportunity for…
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Avionics Integrator Engineer (Hybrid: Montreal, Quebec)
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Aerospace Interiors Design Engineer (Hybrid: Mirabel, Quebec)
Capgemini Engineering
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Added 1 month ago
CE
Analog and RF Layout Engineer
Capgemini Engineering
Toronto, ON
- Full-time
As a Senior Analog / RF IC Layout Engineer, you will play a critical role in designing and enabling cutting‑edge high‑speed mixed‑signal silicon for next‑generation technologies. You will…
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Capgemini Engineering

Analog and RF Layout Engineer

Toronto, ON, Canada

Full-time

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Job details

Job type: Full-time
Experience: 6+ years of experience in Analog, RF, or Mixed-Signal IC Layout.
Posting language: English
Posted: Sep 16, 2026

Original job description

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.

Location

This is a hybrid role based in Toronto, Canada.

About The Job You're Considering

Capgemini Engineering is seeking a Senior Analog / RF IC Layout Engineer to join our growing semiconductor engineering team in the Greater Toronto Area. This is an exciting opportunity for an experienced layout professional who enjoys working on leading-edge mixed-signal and RF integrated circuits in advanced process technologies.

In this role, you will work alongside world-class design and product engineering teams to develop high-performance silicon solutions for next-generation networking, AI, data center, wireless, and communication applications. You will have the opportunity to influence complex designs from architecture through tape-out while contributing to products deployed at global scale.

Your Role

As a Senior Analog / RF IC Layout Engineer, you will:

Lead the physical layout implementation of complex analog, RF, and mixed-signal integrated circuits from concept through tape-out.
Develop and optimize block-level and full-chip layouts in advanced FinFET process technologies, including 7nm and below.
Collaborate closely with Analog, RF, Digital, Physical Design, Verification, and Process teams to achieve aggressive performance, power, area, and yield targets.
Drive floorplanning, device matching, routing strategies, shielding, and critical signal path optimization for high-speed designs.
Implement layout methodologies that address signal integrity, electromigration, IR drop, thermal effects, reliability, and manufacturability requirements.
Perform layout verification, DRC/LVS closure, parasitic extraction review, and tape-out readiness activities.
Support silicon bring-up and debug efforts by partnering with cross-functional engineering teams.
Participate in technical reviews and contribute to layout methodology improvements and best practices.
Mentor junior engineers and provide technical leadership on complex layout challenges.

Required Qualifications

Your Skills and Experience

6+ years of experience in Analog, RF, or Mixed-Signal IC Layout.
Proven experience designing and implementing complex layouts in advanced CMOS and FinFET technologies (7nm and below).
Strong expertise in custom IC layout and physical design methodologies.
Hands-on experience with industry-standard EDA tools from:
- Cadence
- Synopsys
- Siemens EDA (Mentor Graphics)
Experience with advanced matching techniques, symmetry requirements, shielding, guard rings, and high-frequency layout practices.
Knowledge of DRC, LVS, parasitic extraction, and physical verification flows.
Strong understanding of device reliability, electromigration, thermal effects, and manufacturing constraints.

Preferred Experience

Experience developing layouts for one or more of the following:

High-speed SerDes and transceivers
PLLs and clock generation circuits
Data converters (ADC/DAC)
RF front-end circuits
CMOS drivers and receivers
High-speed I/O interfaces
Data center and networking silicon
AI/ML accelerator devices

The base compensation range for this role in the posted location is:70,751 - 165,984.

Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law.

The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction.

These may include, but are not limited to: Geographic location, Education and qualifications, Certifications and licenses, Relevant experience and skills, Seniority and performance, Market and business consideration, Internal pay equity.

It is not typical for candidates to be hired at or near the top of the posted compensation range.

In addition to base salary, this role may be eligible for additional compensation such as variable incentives, bonuses, or commissions, depending on the position and applicable laws.

Capgemini offers a comprehensive, non-negotiable benefits package to all regular, full-time employees. In the U.S. and Canada, available benefits are determined by local policy and eligibility and may include:

Paid time off based on employee grade (A-F), defined by policy: Vacation: 12-25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave
Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)
Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)
Life and disability insurance
Employee assistance programs
Other benefits as provided by local policy and eligibility

Important Notice: Compensation (including bonuses, commissions, or other forms of incentive pay) is not considered earned, vested, or payable until it becomes due under the terms of applicable plans or agreements and is subject to Capgemini’s discretion, consistent with applicable laws. The Company reserves the right to amend or withdraw compensation programs at any time, within the limits of applicable legislation.

Disclaimers

Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. Capgemini also participates in the Partnership Accreditation in Indigenous Relations (PAIR) program which supports meaningful engagement with Indigenous communities across Canada by promoting fairness, accessibility, inclusion and respect. We value the rich cultural heritage and contributions of Indigenous Peoples and actively work to create a welcoming and respectful environment. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.

This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodation does not pose an undue hardship. Capgemini is committed to providing reasonable accommodation during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact.

Please be aware that Capgemini may capture your image (video or screenshot) during the interview process and that image may be used for verification, including during the hiring and onboarding process.

Click the following link for more information on your rights as an Applicant in the United States. http://www.capgemini.com/resources/equal-employment-opportunity-is-the-law

Capgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, generative AI, cloud and data, combined with its deep industry expertise and partner ecosystem.

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More about this job

Responsibilities

Lead the physical layout implementation of complex analog, RF, and mixed-signal integrated circuits from concept through tape-out. Collaborate with cross-functional teams to optimize performance, power, area, and yield while mentoring junior engineers.

Requirements

Requires 6+ years of experience in Analog, RF, or Mixed-Signal IC layout with expertise in advanced FinFET technologies. Candidates must possess strong proficiency in industry-standard EDA tools and physical verification flows.

Skills

Analog IC layout
RF IC layout
Mixed-signal IC layout
FinFET
Cadence
Synopsys
Siemens EDA
DRC
LVS
Parasitic extraction
Floorplanning
Device matching
Electromigration
High-speed design
Shielding
Tape-out

Benefits

Paid time off
Company paid holidays
Personal days
Sick leave
Medical coverage
Dental coverage
Vision coverage
Retirement savings plans
Life insurance
Disability insurance
Employee assistance programs

Visa sponsorship

Not detected in the job text

Keywords

Analog
RF
Mixed-signal
IC Layout
FinFET
Cadence
Synopsys
Siemens EDA
Mentor Graphics
DRC
LVS
Parasitic extraction
Floorplanning
Electromigration
SerDes
PLL
ADC
DAC
CMOS
Semiconductor
Tape-out
Physical design
High-speed I/O
AI/ML accelerator
Networking silicon

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