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Added 1 day ago
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Senior IC Digital Design Engineer
StarIC
Toronto, ON
- Full-time
At StarIC, we’re not just building circuits; we’re shaping the future of technology. As a Toronto-based semiconductor design company, we thrive on creativity, collaboration, and pushing the…
Added 3 days ago
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Field Application Engineer - Emulation
Siemens EDA (Siemens Digital Industries Software)
Ottawa, ON
- Full-time
The Emulation Applications Engineer provides hands-on technical engineering expertise for the implementation, integration, testing, deployment, and support of Siemens EDA hardware-assisted…
Added 3 days ago
Field Application Engineer - Emulation
Siemens
Ottawa, ON
…providing services for the world's largest electronics and semiconductor companies. Continue to learn and support state of the art Siemens EDA emulation tools. This position will provide…
Added 4 days ago
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SoC Design Engineer
Microchip Technology Inc.
Burnaby, BC · Canada - Burnaby
- Full-time
Join the Design Engineering team as Principal Engineer-Design supporting semiconductor architecture, RTL and circuit design, integration, verification, performance, power, area,…
Added 4 days ago
IC
Pre-Si Validation Engineer
Intel Corporation
Toronto, ON · CAN - - Toronto
- Full-time
Join Intel's cutting-edge team as a Formal Verification Engineer, where you will play a pivotal role in ensuring the quality and reliability of our next-generation IP and SoC designs. Your…
Added 9 days ago
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FY27 Intern - Applied AI Engineering Intern (Hardware Systems) - Canada (16 months)
Qualcomm
Vancouver, BC
- Full-time
Our projects span AI-assisted RTL generation and analysis, agentic design automation, functional verification, and intelligent engineering workflows that help shape the future of hardware…
Added 9 days ago
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FY27 Intern - Camera Design Implementation Intern - Canada (16 months)
Qualcomm
Vancouver, BC
- Full-time
…The candidate will be responsible for various functions from RTL integration through physical design. As a member of the Camera team, the successful applicant will help integrate,…
Added 10 days ago
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FY27 Intern - Camera Design Implementation Intern - Canada (16 months)
Qualcomm
Markham, ON
- Full-time
…The candidate will be responsible for various functions from RTL integration through physical design. As a member of the Camera team, the successful applicant will help integrate,…
Added 10 days ago
Q
FY27 Intern - Applied AI Engineering Intern (Hardware Systems) - Canada (16 months)
Qualcomm
Markham, ON
- Full-time
Our projects span AI-assisted RTL generation and analysis, agentic design automation, functional verification, and intelligent engineering workflows that help shape the future of hardware…
Added 10 days ago
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FPGA Designer
Fidus Systems
Canada
- Full-time
…and internal Fidus teams to define architectures, implement RTL, integrate IP, run simulations, close timing, and support lab bring-up and…
Added 10 days ago
Senior ASIC Design Engineer - DSP/Analog/SerDes
Celero Communications, Inc.
Ottawa, ON
Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Our products…
Added 11 days ago
Principal Engineer, CAD
SiTime Corporation
Ottawa, ON
The Principal Engineer, CAD will provide CAD Software support for Digital, Analog and Mixed-Signal designs, using Cadence, Synopsys, Siemens, Keysight & 3rd party vendor tools.…
Added 11 days ago
ASIC Digital Verification Engineer
SiTime Corporation
Ottawa, ON
Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better…
Added 11 days ago
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Sr. Staff Physical Design Engineer
Advanced Micro Devices, Inc
Vancouver, BC
- Full-time
…using advanced process technologies. You will work closely with RTL design and other engineering partners throughout the project lifecycle, from floorplanning, synthesis, and placement…
Added 11 days ago
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ASIC Physical Design, Sr Staff Engineer - 16724
Synopsys Inc
Ottawa, ON · Nepean, ON
- Full-time
…and embedded processors - into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to…
Added 14 days ago
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Staff PCIe Verification Engineer
Arm
Toronto, ON
- Full-time
…level. New team members will join hands with other Architects, RTL design and verification engineers spread across UK, US, Canada and India to build next generation…
Added 14 days ago
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Senior PCIe Verification Engineer
Arm
Toronto, ON
- Full-time
…level. New team members will join hands with other Architects, RTL design and verification engineers spread across UK, US, Canada and India to build next generation…
Added 14 days ago
A
Senior PCIe Design Engineer
Arm
Toronto, ON
- Full-time
Are you ready for a new and exciting challenge? If you are a self-motivated design engineer with expertise in micro-architecture, logic design and ARM IP’s, system protocols and looking to…
Added 15 days ago
MT
LEC (Logic Equivalence Checking) CAD Engineer
Mirafra Technologies
ON · Ontario, Canada
- Full-time
A LEC (Logic Equivalence Checking) CAD Engineer who will develop and support formal equivalence methodologies to ensure functional correctness between RTL, synthesized netlists, and…
Added 15 days ago
Principal Firmware Engineer
Synopsys
Ottawa, ON
Dropping into RTL waveforms to debug firmware comes naturally to you. So does stepping back to question whether the algorithm itself needs rethinking. Profiling compiled code to find…
Added 16 days ago
AM
Firmware Engineering Manager
Advanced Micro Devices, Inc
Markham, ON
- Full-time
…mission spans the full ASIC lifecycle - from architecture and RTL collaboration through emulation, silicon bring-up, production enablement, and customer escalation support. We are…
Added 16 days ago
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FPGA AI Accelerator Engineer
O-HIVE.AI
Windsor, ON
- Full-time
…object detection, and VLM inference into an energy-efficient semiconductor…
Added 16 days ago
A
Firmware Engineering Manager
AMD
Markham, ON
- $140,800 to $211,200 USD / year
- Full-time
…mission spans the full ASIC lifecycle - from architecture and RTL collaboration through emulation, silicon bring-up, production enablement, and customer escalation support. We are…
Added 16 days ago
MT
Computer Aided Design Engineer
Mirafra Technologies
Canada
- Full-time
A LEC (Logic Equivalence Checking) CAD Engineer who will develop and support formal equivalence methodologies to ensure functional correctness between RTL, synthesized netlists, and…
Added 16 days ago
MT
Physical Design Engineer
Mirafra Technologies
Canada
- Full-time
We are seeking a Physical Design Engineer with a strong foundation in Static Timing Analysis (STA) and a focus on design flow automation. In this role, you will be responsible for driving…

Celero Communications, Inc.

Senior ASIC Design Engineer - DSP/Analog/SerDes

Ottawa, ON, Canada

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Job details

Experience: 10+ years of experience in digital ASIC design, with demonstrated ownership of complex ASIC blocks or subsystems.
Posting language: English
Posted: Oct 21, 2026

Original job description

Senior ASIC Design Engineer

Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Our products enable high-performance optical connectivity and next-generation optical transceivers and modems. Celero is seeking a highly skilled and motivated ASIC Design Engineer to join our team and contribute to the development of advanced ASICs for high-speed optical communication systems. The ideal candidate will have strong digital ASIC design expertise combined with hands-on experience in DSP, Analog, and/or SerDes technologies.

Duties & Responsibilities:
• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
• Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.
• Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs.
• Participate in the design and development of high-speed data paths, signal processing blocks, control logic, and interfaces for optical communication systems.
• Perform synthesis, timing analysis, lint, formal equivalence, Clock Domain Crossing (CDC), and related ASIC implementation and signoff activities.
• Optimize designs for performance, power, and area (PPA).
• Perform RTL simulation and debugging to ensure design functionality and performance.
• Contribute to block-level and top-level integration, verification, and silicon bring-up.
• Participate in architecture and design reviews and provide technical guidance to other engineers.
• Collaborate with cross-functional teams to troubleshoot complex design and system-level issues.
• Develop scripts and automation using Python, Tcl, or similar languages to improve design and verification efficiency.
• Contribute to ASIC development from architecture and RTL through tapeout and silicon validation.

Required Qualifications:
• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.
• 10+ years of experience in digital ASIC design, with demonstrated ownership of complex ASIC blocks or subsystems.
• Strong proficiency in Verilog and/or SystemVerilog.
• Strong understanding of digital design principles, RTL design, and ASIC development methodologies.
• Hands-on experience with ASIC design flows and industry-standard EDA tools.
• Strong knowledge of one or more of the following areas:
- Digital Signal Processing (DSP)
- High-speed SerDes
- Analog/Mixed-Signal ICs
- Digital communications
- Optical communications
• Experience working with DSP algorithms, data-path architectures, FEC, equalization, modulation/demodulation, or other high-speed communication technologies.
• Understanding of SerDes architectures and high-speed interfaces, including TX/RX datapaths, equalization, clocking, and related mixed-signal interfaces.
• Experience collaborating with Analog and Mixed-Signal design teams and understanding the interaction between digital, analog, and SerDes blocks.
• Experience with synthesis, static timing analysis, Lint, CDC, formal verification, and RTL simulation.
• Familiarity with verification methodologies such as UVM and/or formal verification.
• Knowledge of low-power design techniques and PPA optimization.
• Strong analytical and problem-solving skills.
• Excellent communication and teamwork skills with the ability to work effectively in a fast-paced startup environment.

Preferred Qualifications
• Experience designing ASICs for optical communications, optical transceivers, coherent communications, or high-speed networking.
• Experience with coherent DSP, FEC, modulation schemes, equalization, or high-speed data recovery.
• Experience with SerDes architectures, including TX/RX, CDR, PLLs, CTLE, DFE, ADC/DAC interfaces, or related high-speed mixed-signal circuitry.
• Experience working with advanced semiconductor process technologies.
• Experience taking ASICs from architecture/RTL through synthesis, physical implementation, tapeout, and silicon bring-up.
• Experience with MATLAB, Python, Tcl, or other modeling and automation tools.
• Understanding of optical communication standards and high-speed networking protocols.
• Experience working in a startup or fast-paced semiconductor development environment.

Why Join Celero?
At Celero, you will have the opportunity to work on challenging, high-performance semiconductor technologies at the intersection of AI infrastructure, optical communications, DSP, SerDes, and mixed-signal design. You will work closely with experienced engineers across multiple disciplines and have the opportunity to make significant contributions to products from architecture through silicon.

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More about this job

Responsibilities

The engineer will design and implement high-performance digital circuits and ASIC blocks for optical communication systems using Verilog and SystemVerilog. They will collaborate with cross-functional teams to integrate DSP, SerDes, and mixed-signal components while optimizing designs for performance, power, and area.

Requirements

Candidates must hold a Master’s or Ph.D. in Electrical or Computer Engineering with over 10 years of experience in digital ASIC design. Strong proficiency in RTL design methodologies, ASIC implementation flows, and expertise in DSP or high-speed SerDes technologies are required.

Skills

Verilog
SystemVerilog
DSP
SerDes
ASIC Design
RTL Design
Static Timing Analysis
Synthesis
CDC
Formal Verification
Mixed-Signal ICs
Python
Tcl
UVM
Low-power design
Silicon bring-up

Visa sponsorship

Not detected in the job text

Keywords

ASIC
DSP
SerDes
Verilog
SystemVerilog
Optical Communications
Mixed-Signal
RTL
Synthesis
Static Timing Analysis
CDC
Formal Verification
UVM
Python
Tcl
MATLAB
Semiconductor
Data Center
AI Infrastructure
FEC
Equalization
Modulation
CDR
PLL
CTLE
DFE
ADC
DAC
Tapeout
Silicon Validation

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