Jobs in Canada

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Added 3 days ago
Senior ASIC Design Engineer - DSP/Analog/SerDes
Celero Communications, Inc.
Ottawa, ON
Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Our products…
Added 9 days ago
Q
Sr ASIC Design Verification Engineer, Low Power AI
Qualcomm
Markham, ON
- Full-time
We are looking for a Senior ASIC Verification Engineer to be part of our team to innovate and design complex leading, ultra-low power, solutions for audio and AI/context aware applications.
Added 9 days ago
ASIC Digital Design, Principal Engineer
Synopsys
Markham, ON
…High-speed SerDes, clock domain crossings that could sink a tapeout, power budgets measured in milliwatts because every one counts. You know that the hardest part of mixed-signal ASIC…
Added 11 days ago
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Senior Embedded Software Engineer
Ranovus
Ottawa, ON
- Full-time
We are seeking a Senior Embedded Software Engineer to work as part of our R&D software-firmware design team.
Added 15 days ago
Q
IC/FPGA Design Verification Engineer, Sr Staff
Qualcomm
Ottawa, ON
- Full-time
…help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP…
Added 19 days ago
AM
Senior Software Engineer - GPU Profiling Tools
Advanced Micro Devices, Inc
Markham, ON
- Full-time
AMD is looking for a Senior Software Engineer - GPU Profiling Tools for the Developer Tools team, where you will contribute to the development and optimization of GPU profiling tools for…
Added 19 days ago
A
Senior Software Engineer - GPU Profiling Tools
AMD
Markham, ON
- $132,000 to $198,000 USD / year
- Full-time
AMD is looking for a Senior Software Engineer - GPU Profiling Tools for the Developer Tools team, where you will contribute to the development and optimization of GPU profiling tools for…
Added 29 days ago
AM
Physical Design Engineer
Advanced Micro Devices, Inc
Markham, ON
- Full-time
…graphics processor IP by driving best‑in‑class Performance, Power, and Area (PPA) outcomes. You will partner closely with RTL, Physical Design, Methodology, and CAD teams to translate…
Added 1 month ago
AM
RTL Design Engineer
Advanced Micro Devices, Inc
Markham, ON
- Full-time
Experience with low-power design techniques and methodologies.
Added 1 month ago
UT
Senior ASIC Verification Engineer
USA Tech Recruit
Ottawa, ON
- $150,000 to $200,000 CAD / year
- Full-time
We are looking for a Senior ASIC Verification Engineer to join a long-term client engagement focused on an advanced I/O chiplet combining die-to-die connectivity with multi-protocol,…
Added 1 month ago
BD
Senior I/O Chiplet RTL Design Engineer
BTA Design Services Inc.
Ottawa, ON
- Full-time
Advanced-node ASIC delivery, low-power design with UPF, or physically aware RTL partitioning
Added 1 month ago
BD
Senior I/O Chiplet Verification Engineer
BTA Design Services Inc.
Ottawa, ON
- Full-time
Headquartered in Ottawa, BTA Design Services supports the electronic design community across Canada and internationally, specializing in ASIC and FPGA design, verification, and embedded…
Added 1 month ago
BD
Senior I/O Chiplet RTL Design Engineer
BTA Design Services
Ottawa, ON
- Full-time
Advanced-node ASIC delivery, low-power design with UPF, or physically aware RTL partitioning.
Added 1 month ago
BD
Senior I/O Chiplet Verification Engineer
BTA Design Services
Ottawa, ON
- Full-time
Headquartered in Ottawa, BTA Design Services supports the electronic design community across Canada and internationally, specializing in ASIC and FPGA design, verification, and embedded…
Added 4 months ago
AM
Physical Design Engineer
Advanced Micro Devices, Inc
Vancouver, BC
- Full-time
…graphics processor IP by driving best‑in‑class Performance, Power, and Area (PPA) outcomes. You will partner closely with RTL, Physical Design, Methodology, and CAD teams to translate…
Added 2 months ago
Q
Engineer
Qualcomm
Markham, ON
- Full-time
QCT's DSP Physical Design Team is seeking motivated and talented Physical Design Engineer to join our growing team in Markham, Canada. In this role, you will contribute to the…
Added 2 months ago
Q
Senior ASIC Implementation Engineer, Low Power AI
Qualcomm
Markham, ON
- Full-time
We are looking for an ASIC Implementation Engineer to be part of our team to innovate and design complex leading, ultra-low power, solutions for audio and context aware applications. We are…
Added 2 months ago
R
SMTS Logic Design
Rambus
Montreal, QC
- Other
As a Senior Member of Technical Staff (SMTS) – Logic Design Engineer, you’ll play a pivotal role in PCIe Gen6/Gen7 switch IP development, contributing to architecture definition,…
Added 2 months ago
Q
Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels)
Qualcomm
Markham, ON
- Full-time
Design high speed, high bandwidth, low power digital hardware solutions using SystemVerilog
Added 2 months ago
Q
Senior Director, Technology
Qualcomm
Ottawa, ON
- Full-time
…help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP…
Added 4 months ago
Q
Systems Architecture, Senior to Staff – Agentic AI
Qualcomm
Markham, Ontario
- Full-time
Be part of the team developing next generation Edge AI subsystems and platforms. The Edge AI Systems Engineer is responsible for system architecture definition activities supporting a…
Added 1 month ago
Sr. Staff ASIC Design Methodology Engineer, AI HW
Tenstorrent Unlisted/Referral Jobs
Toronto, ON
Tenstorrent is seeking a Sr. Staff ASIC Design Methodology Engineer for our AI Hardware Tensix team. In this role, you will advance our design infrastructure and flows across RTL…
Added 4 months ago
Q
Systems Architecture, Senior to Staff – Agentic AI
Qualcomm
Markham, Ontario
- Full-time
Be part of the team developing next generation Edge AI subsystems and platforms. The Edge AI Systems Engineer is responsible for system architecture definition activities supporting a…
Added 4 months ago
Q
Systems Architecture, Senior to Staff – Agentic AI
Qualcomm
Markham, Ontario
- Full-time
Be part of the team developing next generation Edge AI subsystems and platforms. The Edge AI Systems Engineer is responsible for system architecture definition activities supporting a…
Added 4 months ago
Q
Systems Architecture, Senior to Staff – Agentic AI
Qualcomm
Markham, ON
- Full-time
Be part of the team developing next generation Edge AI subsystems and platforms. The Edge AI Systems Engineer is responsible for system architecture definition activities supporting a…

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Celero Communications, Inc.

Senior ASIC Design Engineer - DSP/Analog/SerDes

Ottawa, ON, Canada

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Job details

Experience: 10+ years of experience in digital ASIC design, with demonstrated ownership of complex ASIC blocks or subsystems.
Posting language: English
Posted: Oct 21, 2026

Original job description

Senior ASIC Design Engineer

Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Our products enable high-performance optical connectivity and next-generation optical transceivers and modems. Celero is seeking a highly skilled and motivated ASIC Design Engineer to join our team and contribute to the development of advanced ASICs for high-speed optical communication systems. The ideal candidate will have strong digital ASIC design expertise combined with hands-on experience in DSP, Analog, and/or SerDes technologies.

Duties & Responsibilities:
• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
• Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.
• Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs.
• Participate in the design and development of high-speed data paths, signal processing blocks, control logic, and interfaces for optical communication systems.
• Perform synthesis, timing analysis, lint, formal equivalence, Clock Domain Crossing (CDC), and related ASIC implementation and signoff activities.
• Optimize designs for performance, power, and area (PPA).
• Perform RTL simulation and debugging to ensure design functionality and performance.
• Contribute to block-level and top-level integration, verification, and silicon bring-up.
• Participate in architecture and design reviews and provide technical guidance to other engineers.
• Collaborate with cross-functional teams to troubleshoot complex design and system-level issues.
• Develop scripts and automation using Python, Tcl, or similar languages to improve design and verification efficiency.
• Contribute to ASIC development from architecture and RTL through tapeout and silicon validation.

Required Qualifications:
• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.
• 10+ years of experience in digital ASIC design, with demonstrated ownership of complex ASIC blocks or subsystems.
• Strong proficiency in Verilog and/or SystemVerilog.
• Strong understanding of digital design principles, RTL design, and ASIC development methodologies.
• Hands-on experience with ASIC design flows and industry-standard EDA tools.
• Strong knowledge of one or more of the following areas:
- Digital Signal Processing (DSP)
- High-speed SerDes
- Analog/Mixed-Signal ICs
- Digital communications
- Optical communications
• Experience working with DSP algorithms, data-path architectures, FEC, equalization, modulation/demodulation, or other high-speed communication technologies.
• Understanding of SerDes architectures and high-speed interfaces, including TX/RX datapaths, equalization, clocking, and related mixed-signal interfaces.
• Experience collaborating with Analog and Mixed-Signal design teams and understanding the interaction between digital, analog, and SerDes blocks.
• Experience with synthesis, static timing analysis, Lint, CDC, formal verification, and RTL simulation.
• Familiarity with verification methodologies such as UVM and/or formal verification.
• Knowledge of low-power design techniques and PPA optimization.
• Strong analytical and problem-solving skills.
• Excellent communication and teamwork skills with the ability to work effectively in a fast-paced startup environment.

Preferred Qualifications
• Experience designing ASICs for optical communications, optical transceivers, coherent communications, or high-speed networking.
• Experience with coherent DSP, FEC, modulation schemes, equalization, or high-speed data recovery.
• Experience with SerDes architectures, including TX/RX, CDR, PLLs, CTLE, DFE, ADC/DAC interfaces, or related high-speed mixed-signal circuitry.
• Experience working with advanced semiconductor process technologies.
• Experience taking ASICs from architecture/RTL through synthesis, physical implementation, tapeout, and silicon bring-up.
• Experience with MATLAB, Python, Tcl, or other modeling and automation tools.
• Understanding of optical communication standards and high-speed networking protocols.
• Experience working in a startup or fast-paced semiconductor development environment.

Why Join Celero?
At Celero, you will have the opportunity to work on challenging, high-performance semiconductor technologies at the intersection of AI infrastructure, optical communications, DSP, SerDes, and mixed-signal design. You will work closely with experienced engineers across multiple disciplines and have the opportunity to make significant contributions to products from architecture through silicon.

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More about this job

Responsibilities

The engineer will design and implement high-performance digital circuits and ASIC blocks for optical communication systems using Verilog and SystemVerilog. They will collaborate with cross-functional teams to integrate DSP, SerDes, and mixed-signal components while optimizing designs for performance, power, and area.

Requirements

Candidates must hold a Master’s or Ph.D. in Electrical or Computer Engineering with over 10 years of experience in digital ASIC design. Strong proficiency in RTL design methodologies, ASIC implementation flows, and expertise in DSP or high-speed SerDes technologies are required.

Skills

Verilog
SystemVerilog
DSP
SerDes
ASIC Design
RTL Design
Static Timing Analysis
Synthesis
CDC
Formal Verification
Mixed-Signal ICs
Python
Tcl
UVM
Low-power design
Silicon bring-up

Visa sponsorship

Not detected in the job text

Keywords

ASIC
DSP
SerDes
Verilog
SystemVerilog
Optical Communications
Mixed-Signal
RTL
Synthesis
Static Timing Analysis
CDC
Formal Verification
UVM
Python
Tcl
MATLAB
Semiconductor
Data Center
AI Infrastructure
FEC
Equalization
Modulation
CDR
PLL
CTLE
DFE
ADC
DAC
Tapeout
Silicon Validation

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