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Added 1 min ago
Early Recreation Programs - Lead
Westside Recreation Centre
Calgary, AB
Part-time
The Early Recreation Program Lead is a hands-on supervisory role that is responsible for the development and implementation of Early Recreational Programs (2-6yrs), support Child Minding…
Added 1 min ago
Director Data, AI, and Specialized Business
RBC
Toronto, ON
Full-time
Lead the software development team accountable for a portfolio of vendor applications supporting Specialized Business functions, including release management, configuration, integration,…
Added 1 min ago
Senior Director, AI and Data & Integration Platforms
RBC
Mississauga, ON
Full-time
Enterprise delivery and execution excellence: Demonstrated ability to lead complex, multi-year transformational programs at enterprise scale within financial institutions or regulated…
Added 1 min ago
AI-Native Full Stack Developer - Senior Manager
Accenture
Toronto, ON · Ottawa, ON · Montreal, QC · Vancouver, BC · Calgary, AB
Full-time
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Added 16 mins ago
Material Handler
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Full-time
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Added 16 mins ago
Building Energy Coordinator (EIT)
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Lead the expansion and rollout of the ISO 50001 compliant Energy Management System (EnMS) across 20 additional City of Edmonton facilities, ensuring full compliance with funding agreements
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Test Data Management
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Contract
Able to lead a small team working independently to deliver a feature
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Designer, Development (Service)
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Added 16 mins ago
Mechanical Designer (Fluidpower)
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Industrial Software Validation|
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Internal Auditor (Business Control & IT)
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ERP Business Analyst
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Added 16 mins ago
Senior Conversational AI Engineer/Architect (P4)
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…integration components, and accelerators the team builds from. Lead efforts to improve AI responses, retrieval performance, workflow orchestration, prompt effectiveness, knowledge…
Added 16 mins ago
AI Solution Architect
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$152.13 USD / hour
Other
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Added 16 mins ago
IT Project Manager T2 (CAN)
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Added 16 mins ago
Business Analyst | Must Haves: Requirements Clarification, Stakeholder Comm, Oracle DB | Eval: Agile (30%), Public Sector/Oracle (20%), DevOps (10%)
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…Unified Project Management Methodology and OPS Standard Systems Development Methodologies Develops strategies, prepares business cases and cost-benefit analysis, and conducts feasibility…
Added 16 mins ago
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VP, Quantitative Research (Public Affairs/Online Communities)
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Support Engineer (Site Reliability Engineering (SRE) E3)
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Cerebras

FPGA Engineer

Toronto, ON, Canada

Job type: Full-time
Apply by: Oct 2, 2026
Experience: 5+ years industry experience generating production FPGA solutions, OR Master's/PhD in Computer or Electrical Engineering + 3 years industry experience,
Posting language: English
Posted: Sep 23, 2026

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Original job description

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.

This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.

Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.

About The Role

The Host and Network IO Team develops the full IO path implementation between a distributed system of server nodes, through the cluster, down to the custom RoCE network stack implemented in Cerebras' system, and over the proprietary IOs onto the WSE. As an FPGA developer on the team, you will own the in-chassis IO subsystem consisting of i) several cluster-facing RoCE v2 network interfaces via a custom implementation of the RDMA protocol; ii) a large programmable switching fabric; and iii) Serial IO communication with the Cerebras WSE via a proprietary protocol. You will interface between AI application-level IO teams, cluster architecture teams, and embedded software teams to develop solutions that optimize bandwidth and latency while minimizing congestion, pauses, pause spreading, unfairness, etc. The scope of work spans multiple generations of hardware products from improvements to presently deployed hardware, implementation of upcoming systems, and design/architecting of future next-gen architectures.

Responsibilities

Lead full chassis-to-wafer IO architecture and design
Improve current RTL, implement next-gen FPGA design, define future IO architectures
Produce production-ready bitstreams for deployment into large clusters running customer inference services
Work with DV team to prevent bug slips and simplify debug
Optimize bandwidth/latency over FPGA datapath and all IO interfaces
Interface with board team facilitating and executing board bringup
Drive network performance debug of large AI clusters
Integrate leading edge networking technologies and protocols
Lead cross-functional technical projects spanning multiple teams and integrating diverse software and hardware components to deliver an improved network IO solution.
Foster clear and effective communication across teams and stakeholders.

Skills & Qualifications

5+ years industry experience generating production FPGA solutions, OR Master's/PhD in Computer or Electrical Engineering + 3 years industry experience,
Proficiency in Verilog development in Git based repo
Highly productive with FPGA placement & routing, timing closure, simulation, debug, and other FPGA tools/workflows
Network protocol familiarity (TCP, RoCE) and network debug tools such as Wireshark
Knowledge of network switch environments or willingness to learn (Arista, Juniper, etc.).
AI-augmented development environment

Why Join Cerebras

About

People who are serious about software make their own hardware. At Cerebras, we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras:

Build a breakthrough AI platform beyond the constraints of the GPU.
Publish and open source their cutting-edge AI research.
Work on one of the fastest AI supercomputers in the world.
Enjoy job stability with startup vitality.
Our simple, non-corporate work culture that respects individual beliefs.

Find out more about what it's like to work at Cerebras here!

Apply today and become part of the forefront of groundbreaking advancements in AI!

Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.

This website or its third-party tools process personal data. For more details, click here to review our CCPA disclosure notice.

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More about this job

Responsibilities

Lead the architecture, design, and implementation of chassis-to-wafer I/O systems, including RoCE network interfaces, programmable switching, and serial communication with Cerebras wafers. Deliver production FPGA bitstreams, optimize network performance, support board bring-up and cluster debugging, and coordinate technical work across hardware and software teams.

Requirements

Candidates need at least five years of industry experience producing FPGA solutions, or a master's or PhD in Computer or Electrical Engineering plus at least three years of industry experience. They should be proficient in Verilog and Git-based development, FPGA implementation and debug workflows, and network protocols such as TCP and RoCE; familiarity with network switches and tools such as Wireshark is also sought.

Skills

FPGA Development
Verilog
RTL Design
FPGA Placement And Routing
Timing Closure
Simulation And Debugging
RoCE
TCP
RDMA
Network Protocols
Network Debugging
Wireshark
Git
Board Bring-Up
Bandwidth And Latency Optimization
Cross-Functional Project Leadership

Visa sponsorship

Not detected in the job text

Keywords

FPGA
Verilog
RTL
RoCE V2
RDMA
TCP
Network I/O
Programmable Switching Fabric
Serial I/O
Cerebras Wafer-Scale Engine
FPGA Placement And Routing
Timing Closure
Simulation
Debugging
Git
Wireshark
Network Switches
Arista
Juniper
Board Bring-Up
Network Performance
Bandwidth Optimization
Latency Optimization
Congestion Management
Production Bitstreams
AI Infrastructure
Cluster Architecture
Hardware-Software Integration
Network Protocols
AI-Augmented Development

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