Physical Design Engineer
- Vancouver, BC, Canada
Contract
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Job details
- Job type
- Contract
- Apply by
- Experience
- ✅ 5+ years of hands-on ASIC physical design and implementation experience
- Posting language
- English
- Posted
Original job description
🚀 We’re Hiring: Physical Design Engineer (ASIC)
📍 Vancouver, BC, Canada (Onsite)
📄 Contract: 12–18 months
We’re hiring a Physical Design Engineer for a leading global networking and semiconductor company. You’ll join an ASIC Physical Design team and own full-chip physical implementation from RTL to GDSII on advanced technology nodes.
What you’ll do
🔹 Own physical design implementation of multi-hierarchy designs: physical-aware synthesis, DFT, floorplanning, placement, CTS and routing
🔹 Drive Static Timing Analysis (STA) and timing signoff closure
🔹 Perform IR Drop/EM analysis and physical verification (DRC/LVS) through signoff
🔹 Optimize designs for Power, Performance and Area (PPA)
🔹 Work with Front-End/RTL teams to understand the design architecture and resolve implementation issues
🔹 Build and improve automation scripts and physical design flows
What we’re looking for
✅ BS/MS in Electrical Engineering, Computer Engineering or Computer Science
✅ 5+ years of hands-on ASIC physical design and implementation experience
✅ Strong skills in floorplanning, PnR, CTS, timing closure and hierarchical design
✅ Hands-on experience with industry-standard EDA tools (Synopsys, Cadence; Calibre/ICV for PV)
✅ Experience with EM/IR and physical verification signoff
✅ Scripting in Tcl, Python or Perl
✅ Eligible to work in Canada
Nice to have
➕ Formal verification (LEC) experience
➕ Experience with advanced nodes (5nm/3nm) and complex SoC integration
📩 Interested? DM me or comment “Interested” and I’ll reach out. Referrals are welcome!
Equal Employment Opportunity: We are an equal opportunity employer. All qualified applicants will be considered for employment without regard to race, colour, religion, sex, sexual orientation, gender identity or expression, national origin, age, disability, Indigenous status, veteran status, or any other characteristic protected by applicable law. We are committed to an inclusive and accessible hiring process. Accommodations are available on request at any stage.
#Hiring #PhysicalDesign #ASIC #VLSI #Semiconductor #RTLtoGDSII #STA #VancouverJobs #CanadaJobs #ContractJobs #HardwareEngineering
More about this job
Responsibilities
Own full-chip ASIC physical implementation from RTL to GDSII, including synthesis, DFT, floorplanning, placement, clock tree synthesis, routing, and timing signoff. Perform power, performance, and area optimization, IR drop and EM analysis, physical verification, and collaborate with RTL teams while improving automation scripts and design flows.
Requirements
Requires a bachelor's or master's degree in Electrical Engineering, Computer Engineering, or Computer Science, at least five years of hands-on ASIC physical design experience, and eligibility to work in Canada. Candidates should have strong implementation and timing-closure skills, experience with industry-standard EDA and physical verification tools, and scripting ability; formal verification and advanced-node experience are advantageous.
Skills
- ASIC Physical Design
- Physical-Aware Synthesis
- DFT
- Floorplanning
- Placement
- Clock Tree Synthesis
- Routing
- Static Timing Analysis
- Timing Closure
- IR Drop and EM Analysis
- Physical Verification
- DRC/LVS
- PPA Optimization
- Tcl
- Python
- Perl
Visa sponsorship
Not detected in the job text
Categories
- Engineering
- Technology
Keywords
- ASIC
- Physical Design
- RTL To GDSII
- Physical-Aware Synthesis
- DFT
- Floorplanning
- Placement
- Clock Tree Synthesis
- Routing
- Static Timing Analysis
- Timing Signoff
- Timing Closure
- IR Drop
- Electromigration
- DRC
- LVS
- Power, Performance, And Area
- Synopsys
- Cadence
- Calibre
- ICV
- Tcl
- Python
- Perl
- Formal Verification
- LEC
- Advanced Technology Nodes
- 5nm
- 3nm
- SoC Integration