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Added 2 mins ago
Senior Data Engineer
Fraser Health
Surrey, BC
Full-time
…department of Fraser Health, we are looking for a Senior Data Engineer to join our agile and fast paced team. Reporting to the Director, Data Engineering, this position is part of the team…
Added 2 mins ago
Technical Sales Representative
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Full-time
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Added 2 mins ago
Field Coordinator Co-Op / Internship | January 2027
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Vancouver, BC
Assist with project start-up activities and provide support to Project Engineer, Project Superintendent, and/or Project Manager.
Added 17 mins ago
Water Resources Engineering Graduate
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Full-time
An opportunity exists within Stantec’s Land Services Team for a Water Resources Engineer, Certified Engineering Technologist or Engineering Graduate. The position will be based out of the…
Added 17 mins ago
Technical Project Manager
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Full-time
…execution from kickoff through go-live. You don't need to be an engineer, but you should understand how systems connect and be able to translate a client's operational reality into scope…
Added 17 mins ago
Data Scientist II
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Added 17 mins ago
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Added 17 mins ago
Release Train Engineer II
TD
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Added 31 mins ago
Lead/ Senior Power Systems Engineer
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Added 31 mins ago
Field Services Engineer
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Vancouver, BC
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Added 31 mins ago
Environmental Engineer / Geoscientist
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Added 31 mins ago
Environmental Engineer / Geoscientist
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Added 31 mins ago
Senior Piping Designer CAN
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Added 31 mins ago
RF Engineer (French)
Apptoza Inc.
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Contract
Added 31 mins ago
Environmental Engineer / Geoscientist
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Added 31 mins ago
Python/Spark Developer
Procom
Mississauga, ON
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Seeking a Core Python Engineer with expertise in big data processing, particularly within the TechFin industry. This role involves developing and optimizing data pipelines for credit risk…
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Lead Electrical Engineer, Mission Critical & Data Centers
WSP in Canada
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Join our Mission Critical & Data Centers team as a Lead Electrical Engineer and help shape the future of digital infrastructure across Canada. This is an opportunity to lead the design and…
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Principal Consultant, Environmental Acoustics
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…registered, or eligible for registration, as a Professional Engineer (P.Eng.) with Engineers and Geoscientists…
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Environmental Engineer / Geoscientist
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Added 31 mins ago
Technology Commercialization Executive
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Full-time
You have worked in ambiguity - as a product lead, founding PM, co-founder, applications or solutions engineer, or the first commercial hire at an early-stage company.
Added 31 mins ago
Administrator
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AB · Edmonton, AB
Full-time
Innovation- if it doesn’t exist, we will engineer and manufacture it
Added 31 mins ago
Rendering Engineer Intern
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Vancouver, BC · Greater Vancouver Metropolitan Area
Temporary
We are opening a unique opportunity for a Rendering Engineer Intern to join the Apex Legends team based in Vancouver!
Added 31 mins ago
AI/ML Data Engineer
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AI Engineer Intern – Creative Innovations (Character Pipelines)
Added 31 mins ago
Data Engineer
MSi Corp
Montreal, QC
Contract
We are looking for a Data Engineer to join our telecom clients BI group. In this role, you will build scalable ingestion frameworks and reliable data pipelines across cloud ecosystem,…

Ciena

ASIC Engineer Intern

Ottawa, ON, Canada

Pay: The hourly pay range for this position is $25.50 - $35.00.
Job type: Full-time
Posting language: English
Posted: Sep 22, 2026

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Original job description

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being - on and off the job. Connect with a career that matters.

The Opportunity: Work term of 4 months extendable to 8, starting in January 2027.

Ciena is seeking a student to contribute to the development and evolution of automation infrastructure used for next-generation ASIC devices. The role provides exposure to ASIC design, integration, layout, and verification activities within large-scale DSP ASIC development for optical communications. The position is aligned to a student’s experience, strengths, and technical interests.

How you will make an impact:

Contribute to the development of automation infrastructure for ASIC devices.
Collaborate with developers and team leads to advance ASIC design, layout, integration, and verification activities.
Develop design blocks and evaluate designs for correctness and performance.
Implement netlists into silicon-realizable layouts and automate placement and extraction workflows.
Create constraints, analyze implementation reports, and automate ASIC integration processes.
Develop reusable SystemVerilog/UVM verification components.
Enhance Python-based reporting, analysis, build, simulation, and debug workflows.

The must haves:

Programming experience using one or more of Java, Python, TCL, Skill/Ocean, or SystemVerilog.
Familiarity with Linux-based development environments.

Nice to haves:

Previous experience with ASIC or FPGA development programs.
Strong analytical and debugging skills.
Familiarity with Agile, JIRA, Confluence, and Git.

Pay Range:

The hourly pay range for this position is $25.50 - $35.00.

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation pay as required by applicable laws.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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More about this job

Responsibilities

The intern will contribute to the development and evolution of automation infrastructure for next-generation ASIC devices. Responsibilities include collaborating on ASIC design, layout, integration, and verification activities while enhancing Python-based workflows.

Requirements

Candidates must have programming experience in languages such as Java, Python, TCL, or SystemVerilog and familiarity with Linux environments. Previous experience with ASIC or FPGA development programs is considered a strong asset.

Skills

Java
Python
TCL
Skill/Ocean
SystemVerilog
Linux
ASIC design
FPGA development
Debugging
Agile
JIRA
Confluence
Git
Verification
Layout
Integration

Benefits

Employee Assistance Program
Company-paid holidays
Paid sick leave
Vacation pay

Visa sponsorship

Not detected in the job text

Keywords

ASIC
FPGA
Automation
Infrastructure
DSP
Optical communications
SystemVerilog
UVM
Python
Java
TCL
Linux
Agile
JIRA
Confluence
Git
Verification
Layout
Netlists
Silicon
Placement
Extraction
Constraints
Debugging
Connectivity
Networking
Hardware design

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