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Added 7 hours ago
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Principal SerDes System/DSP Design Engineer
Ciena
Canada
- $126,100 to $201,500 CAD / year
- Full-time
Experience with MATLAB, Python, or C/C++ for algorithm design and simulation.
Added 8 hours ago
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Ciena

Principal SerDes System/DSP Design Engineer

Canada

$126,100 to $201,500 CAD / year · Full-time

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Job details

Pay: $126,100 to $201,500 CAD / year
Job type: Full-time
Experience: 8+ years of experience in high-speed serial link or communication system design.
Posting language: English
Posted: Sep 20, 2026

Original job description

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity - driving our business priorities alongside meaningful social, community, and societal impact.

We’re building the next generation of 448G electrical SerDes and pioneering optical IMDD systems to power tomorrow’s networks. Our engineering team lives at the intersection of high-performance DSP design, system modeling, and optical innovation.

How You Will Contribue

We are seeking a highly skilled Senior SerDes System/DSP Design Engineer to join our advanced engineering team . In this role, you will lead the architecture, design, and validation of high-speed serial transceivers across electrical and optical domains. You will leverage your expertise in systems engineering, control theory, DSP algorithms, and modeling to develop cutting-edge serial electrical/optical-IMDD transceiver solutions.

This position offers the opportunity to work on industry-leading designs at the intersection of electrical SerDes technology and advanced optical communications, driving innovations that enable next-generation high-capacity networks.

Lead the design and development of electrical SerDes DSP architectures for high-speed data communication systems.
Perform system-level evaluation, modeling, and performance analysis of SerDes transceiver solutions including impairments and mitigation techniques.
Develop algorithms and architectures for adaptive equalization, maximum likelihood sequence detection (MLSD), and timing recovery algorithms.
Integrate control theory and advanced DSP designs into feasible hardware implementations.
Collaborate with cross-functional teams (analog design, ASIC design, electro-optical hardware, firmware) to optimize SerDes performance in end-to-end systems.
Conduct design trade-offs to meet stringent performance, power, and area targets.
Analyze channel models, analog circuits impairments (DAC, ADC, AFE, …) and system constraints to determine system level margin and FEC (forward error correction) performance and optimize system margin.
Provide system level specifications for different sub-blocks of SerDes transceivers such as DAC, ADC, AFE, PLL.
Evaluate and model IMDD optical links and formulate strategies to enhance system robustness.
Document design specifications, system performance results, and contribute to IP generation and innovation roadmaps.

The Must Haves

Advanced expertise in electrical SerDes DSP design and implementation.
Proven experience in SerDes system-level evaluation, modeling, and simulation.
Strong proficiency in control theory and digital signal processing (DSP) applied to high-speed communication systems.
Familiarity with optical IMDD (Intensity Modulation Direct Detection) systems.
Deep understanding of adaptive equalization techniques for high-speed links.
Proficiency with maximum likelihood sequence detection (MLSD) approaches.
Expertise in timing recovery schemes in high-speed serial links.
Practical knowledge of FEC performance modeling and system-level performance optimization.
Experience with MATLAB, Python, or C/C++ for algorithm design and simulation.
Strong problem-solving skills and ability to work across hardware/software boundaries.
Ph.D. in Electrical Engineering with background in digital communications and signal processing.
8+ years of experience in high-speed serial link or communication system design.

Nice To Haves

Knowledge of industry standards such as PCIe, IEEE, Ethernet, or OIF standards for optical communication.
Hands-on experience with lab bring-up, characterization, and debugging of SerDes links.

Pay Range

The annual salary range is $126,100 - $201,500 CAD.

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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More about this job

Responsibilities

Lead the architecture, design, modeling, and validation of high-speed electrical SerDes and optical IMDD transceiver systems, including DSP algorithms for equalization, sequence detection, and timing recovery. Analyze channel and circuit impairments, optimize system margin and FEC performance against power and area targets, define sub-block specifications, and collaborate across hardware and software teams.

Requirements

Requires a Ph.D. in Electrical Engineering focused on digital communications and signal processing, at least 8 years of high-speed serial link or communication system design experience, and advanced expertise in SerDes DSP, system modeling, control theory, equalization, MLSD, timing recovery, and FEC performance. Candidates should be proficient in MATLAB, Python, or C/C++, understand optical IMDD systems, and be able to work across hardware and software boundaries.

Skills

Electrical SerDes DSP Design
SerDes System Modeling
Digital Signal Processing
Control Theory
Adaptive Equalization
Timing Recovery
FEC Performance Modeling
Optical IMDD Systems
MATLAB
Python
C/C++
System-Level Simulation
Channel Modeling
Hardware-Software Integration
Lab Characterization and Debugging

Benefits

Medical Insurance
Dental Insurance
Vision Insurance
401(k)
Employee Stock Purchase Program
Employee Assistance Program
Company-Paid Holidays
Paid Sick Leave
Vacation Time
Paid Family Leave

Visa sponsorship

Not detected in the job text

Keywords

SerDes
448G Electrical SerDes
Digital Signal Processing
Control Theory
System Modeling
System-Level Evaluation
Adaptive Equalization
Timing Recovery
Optical IMDD
Forward Error Correction
FEC Performance
Channel Models
DAC
ADC
AFE
PLL
MATLAB
Python
C/C++
ASIC Design
Analog Design
Electro-Optical Hardware
Firmware
PCIe
IEEE
Ethernet
OIF Standards
Lab Bring-Up

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