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Principal/Team Lead, Digital Verification Engineer (FEC)
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- $136,700 to $218,300 CAD / year
- Full-time
…Ciena’s Forward Error Correction (FEC) IP. Reporting to the ASIC Senior Manager, you will collaborate with a team of Digital Design Engineers, Verification Engineers, and Architects to…
Added 1 hour ago
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Ciena

Principal/Team Lead, Digital Verification Engineer (FEC)

Ottawa, ON, Canada

$136,700 to $218,300 CAD / year · Full-time

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Job details

Pay: $136,700 to $218,300 CAD / year
Job type: Full-time
Experience: 10+ years of experience in verification.
Posting language: English
Posted: Nov 5, 2026

Original job description

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being - on and off the job. Connect with a career that matters.

Job Description

How You Will Contribute:
At Ciena, we are at the forefront of the telecommunications industry, and our Wavelogic modem family of products plays a crucial role in our success. As a Digital Verification Engineer (FEC), you will be an integral part of a team responsible for implementing innovative verification strategies in order to thoroughly simulate and validate functional blocks and subsystems for Ciena’s Forward Error Correction (FEC) IP. Reporting to the ASIC Senior Manager, you will collaborate with a team of Digital Design Engineers, Verification Engineers, and Architects to simulate and validate functional blocks and subsystems.

Responsibilities:

Read and understand the FEC architecture and functional requirements specification document(s) and communicate and collaborate with FEC designers, DSP modelers, FEC verifiers, systems engineers and architects.
You will be responsible for developing verification, functional coverage and formal verification test plans.
Thoroughly validate one or more architectural FEC functional blocks using a combination of simulation, formal, and coverage methods.
Create testbench environments and components, agents, scoreboard, and test scenarios using System Verilog UVM and C++.
Perform coverage-driven verification, monitor regressions, and debug failures with the support of the function's designer.
Provide status updates on verification progress on a regular basis and communicate risks as needed.
Mentor and supervise junior verification engineers requiring robust understanding of team outputs to foster peers’ technical and professional growth
Excellent communication and interpersonal skills with demonstrated ability to convey complex technical concepts clearly and effectively influence stakeholders
We expect you to have:
- Detail-oriented – Deliver on objectives through meticulous, thorough, and comprehensive work.
- Problem solver – Analyze and solve complex technical problems using engineering principles.
- Commitment to learning – Keep abreast of technology developments and are keen to share your knowledge with others.

The Must Haves:

10+ years of experience in verification.
Minimum Bachelor's degree in Electrical, Computer or Software Engineering.
Significant experience in using C/C++, System Verilog, UVM, SVA, and simulators from major vendors.
Proven ability to determine comprehensive digital verification and coverage strategies
Proven ability to foster a culture of innovation and continuous improvement within the team via demonstrated leadership and communication capabilities
Strong decision-making skills with the ability to analyze complex situations, evaluate options and implement effective solutions to meet deliverables.

Assets:

Experience with formal verification methods.
Strong background in Forward Error Correction (FEC) and/or DSP.
Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++.
Proficiency in bug tracking using Jira and source code management and revision tracking using GIT.
Previous experience leading a team.
Previous experience mentoring.

Pay Range: The annual salary range for this position in Ottawa is $136,700 - $218,300 CAD.

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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More about this job

Responsibilities

You will lead the development of verification strategies and test plans to validate functional blocks for Ciena's Forward Error Correction IP. Additionally, you will mentor junior engineers and collaborate with cross-functional teams to ensure high-quality design outcomes.

Requirements

Candidates must have at least 10 years of experience in digital verification and a Bachelor's degree in Electrical, Computer, or Software Engineering. Proficiency in System Verilog, UVM, and C++ is essential, along with strong leadership and problem-solving capabilities.

Skills

Digital verification
System Verilog
UVM
C++
Forward Error Correction
DSP
Formal verification
Functional coverage
Testbench development
Regression monitoring
Debugging
Leadership
Mentoring
Communication
ASIC verification
SVA

Benefits

Medical plan
Dental plan
Vision plan
DCPP with company matching
Employee Stock Purchase Program
Employee Assistance Program
Company-paid holidays
Paid sick leave
Vacation time
Paid Family Leave

Visa sponsorship

Not detected in the job text

Keywords

Digital Verification
FEC
ASIC
System Verilog
UVM
C++
DSP
Formal Verification
SVA
Functional Coverage
Testbench
Jira
GIT
Telecommunications
Networking
Hardware Engineering
Regression
Debugging
Leadership
Mentoring
Python
Bash
Object-oriented programming
Architecture
Connectivity
AI era
Infrastructure
Verification Strategy
Simulation
Design Engineering

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