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Added 9 mins ago
Project Coordinator
Pomerleau
Gagetown, NB
Full-time
Pomerleau is a national leader in construction, delivering major projects across Canada. We believe in creating a workplace where people feel respected, supported, and empowered to grow.…
Added 9 mins ago
Associate Director, Quality Systems & Compliance
Tundra Technical Solutions
Toronto, ON · Greater Toronto Area, Canada
$132,240 to $165,300 CAD / year
Full-time
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Ciena

Senior ASIC Verification Engineer, onsite Kanata

Ottawa, ON, Canada

Pay: $109,000 to $174,000 CAD / year
Job type: Full-time
Posting language: English
Posted: Sep 30, 2026

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Original job description

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being - on and off the job. Connect with a career that matters.

The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for a hardworking digital verification engineer who will be involved in the verification of these products, working within a team of digital design engineers, verification engineers and architects.

Your role as a digital verification engineer will be to propose and implement innovative verification strategies, in order to thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family of products.

As a digital verification engineer, you are encouraged to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects

You are held responsible for the complete and thorough validation of one or more architectural functional blocks by using an appropriate combination of simulation, formal and coverage methods

You are encouraged the build the verification, functional coverage and formal verification test plans

You are accountable for the creation of testbench environment and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable

You will perform coverage driven verification, formal verification, monitor regressions and debug resulting failures with the help of the function's designer

Reporting status updates on a regular basis

The Must Haves:

Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc or MEng/MSc level

A highly motivated self-starter, able to work independently, while being a great teammate

Ability to methodically tackle sophisticated technical problems

Excellent organization, written and oral (English) interpersonal skills

Familiarity with formal verification methods

Familiarity with standards and protocols such as OTN, B100G, Ethernet

Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++, System C

The above lists are intended to describe the general nature and level of work, and they are not intended to be a comprehensive list of all responsibilities, duties and skills required to be qualified and to be performed by the selected candidate. You will have an opportunity to better understand the role through the interview experience.

Pay Range

The annual salary range for this position is $109,000 - $174,000 CAD.

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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More about this job

Responsibilities

The engineer will implement innovative verification strategies and create testbench environments to validate functional blocks for the Wavelogic product family. They are responsible for building test plans, performing coverage-driven and formal verification, and debugging failures in collaboration with design teams.

Requirements

Candidates must hold a degree in electrical engineering, computer engineering, or computer science. Proficiency in System Verilog, UVM, and formal verification methods is required, along with familiarity with networking protocols like OTN and Ethernet.

Skills

ASIC Verification
System Verilog
UVM
Formal Verification
Functional Coverage
Python
C
C++
System C
OTN
Ethernet
B100G
Testbench Development
Debugging
Architecture Analysis

Benefits

Medical plan
Dental plan
Vision plan
DCPP with company matching
Employee Stock Purchase Program
Employee Assistance Program
Company-paid holidays
Paid sick leave
Vacation time
Paid Family Leave

Visa sponsorship

Not detected in the job text

Keywords

ASIC
Verification
System Verilog
UVM
Formal Verification
Functional Coverage
OTN
B100G
Ethernet
Python
C
C++
System C
Testbench
Scoreboard
Regression
Optical Fiber
Telecommunications
Networking
Hardware Engineering
Digital Design

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