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Database developer Smartstream TLM SME Senior Engineer
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Ciena

Senior Digital ASIC Verification Engineer

Ottawa, ON, Canada

$111,900 to $178,700 CAD / year · Full-time

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Applications open in a new tab.

Job details

Pay: $111,900 to $178,700 CAD / year
Job type: Full-time
Experience: 5+ years of relevant experience in digital ASIC/SoC verification, with demonstrated experience independently verifying complex designs.
Posting language: English
Posted: Nov 4, 2026

Original job description

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being - on and off the job. Connect with a career that matters.

How You Will Contribute

We are looking for an experienced Senior Digital ASIC Verification Engineer to join our top-level team. You will play a key role in verifying complex, highly integrated digital ASICs, with a particular focus on top-level functionality, cross-IP interactions, and system-level use cases.

In this role, you will take ownership of complex verification activities, working closely with digital designers, architects, and verification engineers to develop verification strategies, create functional test environments and scenarios, debug challenging failures, and drive verification toward closure.

This is a role for an engineer who can independently tackle complex verification problems while providing technical guidance and contributing to improvements in the team's verification methodology and efficiency.

What You Will Do:

Take ownership of complex top-level and cross-IP verification activities, from verification planning through execution, debug, coverage analysis, and closure.
Develop and maintain SystemVerilog/UVM functional verification environments, testbenches, testcases, checkers, assertions, and supporting verification infrastructure.
Develop cross-IP and system-level test scenarios that exercise interactions, data flows, and dependencies across multiple functional blocks.
Translate architecture, design specifications, and system requirements into comprehensive verification plans and test strategies.
Work closely with designers, architects, and verification engineers to identify verification risks, corner cases, and potential gaps early in the development cycle.
Integrate and reuse block-level verification components within subsystem and top-level verification environments.
Apply formal verification techniques where appropriate, including developing assertions and properties to complement simulation-based verification and improve overall verification coverage.
Clearly communicate verification status, risks, issues, and recommendations to the broader ASIC development team.
Mentor and provide technical guidance to junior engineers.

The Must Haves

5+ years of relevant experience in digital ASIC/SoC verification, with demonstrated experience independently verifying complex designs.

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.

Strong hands-on experience with SystemVerilog and UVM.

Experience developing verification plans and translating design and architectural requirements into testcases.

Strong analytical, problem-solving, communication, and collaboration skills.

Nice to Haves

Experience with formal verification, including property checking, assertion-based verification, formal applications, or formal coverage techniques.

Experience writing SystemVerilog Assertions (SVA).

Experience verifying large ASICs or SoCs at the subsystem or chip/top level.

Experience with scripting and automation using Python, Bash, Make, or similar tools.

Familiarity with high-speed networking or communications technologies such as Ethernet or OTN.

Pay Range: The annual salary range for this position is $111,900 - $178,700 CAD.

Requisition Status: Future Vacancy

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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More about this job

Responsibilities

You will lead complex top-level and cross-IP verification activities, including planning, execution, and debugging for digital ASICs. Additionally, you will develop functional test environments and mentor junior engineers to ensure verification closure.

Requirements

Candidates must have at least 5 years of experience in digital ASIC/SoC verification and strong proficiency in SystemVerilog and UVM. A Bachelor's or Master's degree in Electrical or Computer Engineering is required.

Skills

SystemVerilog
UVM
ASIC Verification
SoC Verification
Functional Verification
Verification Planning
Debugging
Coverage Analysis
System-level testing
Formal Verification
SVA
Python
Bash
Make
Networking
Ethernet

Benefits

Medical plan
Dental plan
Vision plan
DCPP with company matching
Employee Stock Purchase Program
Employee Assistance Program
Company-paid holidays
Paid sick leave
Vacation time
Paid Family Leave

Visa sponsorship

Not detected in the job text

Keywords

ASIC
SoC
Verification
SystemVerilog
UVM
Digital Design
Formal Verification
SVA
Python
Bash
Make
Ethernet
OTN
Connectivity
Networking
Testbench
Functional Coverage
Debugging
Architecture
Hardware Engineering

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