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Added 12 mins ago
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Ciena

Senior Manager, Layout Design

Ottawa, ON, Canada

Pay: Pay Range: $171,200 - $273,400 CAD
Job type: Full-time
Experience: 15+ years of layout experience
Posting language: English
Posted: Sep 23, 2026

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Original job description

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being - on and off the job. Connect with a career that matters.

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity - driving our business priorities alongside meaningful social, community, and societal impact.

This is a senior layout design manager position. In this role you and your team will lead design enablement of advanced high-speed analog circuits in the latest deep-submicron CMOS and/or BiCMOS technologies. You’ll drive and implement best-in-class high-speed analog layouts that extract the highest performance from the world’s most advanced CMOS and BiCMOS technologies. These analog macros include electrical interface-facing DAC and ADC based SERDES solutions for 112G and 224G, optical-line-facing high-speed DAC and ADC circuits working with optical modulators and detectors, transimpedance amplifiers, modulator driver circuits, and critical precision analog circuits for control and monitoring functions.

How Will You Contribute

Work closely with Ciena’s international layout, circuit design, and packaging groups across different time zones and regions.
Plan and schedule projects to ensure successful delivery while maintaining a healthy work–life balance for the team.
Lead Block and Macro level layout development including floor-planning, layout creation and optimization.
Perform feasibility work with various circuit topologies working with senior analog designers to achieve a best-in-class solutions to carry through detailed implementation by weighing tradeoffs and discussing these with other members of the team.
Undertake physical verification and electromigration checks
Perform PERC verification and debugging for ESD structures.
Automate layout flows with scripts and pcells.
Develop and implement template-based layout methodology.
Provide status updates on a regular basis, participate in team meetings and share experience with the broader team.
Mentor junior team members and co-op students

Must Haves

15+ years of layout experience
Bachelor’s degree in electrical or computer engineering, computer science, or in a related field.
Proven experience in leading analog high-speed layout design within advanced BiCMOS and/or CMOS technologies, with years of industry experience.
Successful experience in managing and delivering MPWs, test chips, and product chips.
Ability to thoroughly understand challenging design rules from leading-edge manufacturing processes.
Proficient in reading and debugging Calibre/ICV verification decks.
Highly motivated self-starter with the ability to work independently while also contributing effectively as part of a team.
Demonstrated ability to methodically solve complex technical challenges.
Strong organizational, written, and verbal communication skills.
Advanced proficiency with industry-standard analog design tools such as Cadence, Mentor, and Synopsys (e.g., Virtuoso, Calibre).

Pay Range: $171,200 - $273,400 CAD

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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More about this job

Responsibilities

Lead the layout development of advanced high-speed analog circuits, including floor-planning and optimization for complex macros. Collaborate with international design teams to ensure successful project delivery while mentoring junior staff.

Requirements

Requires 15+ years of layout experience and a bachelor's degree in electrical or computer engineering. Must possess proven expertise in high-speed analog layout within advanced CMOS/BiCMOS technologies and proficiency in industry-standard design tools.

Skills

Layout design
High-speed analog circuits
CMOS
BiCMOS
SERDES
DAC
ADC
Floor-planning
Physical verification
Electromigration checks
PERC verification
ESD structures
Cadence
Mentor
Synopsys
Virtuoso

Benefits

Medical plan
Dental plan
Vision plan
401(k) matching
DCPP matching
Employee Stock Purchase Program
Employee Assistance Program
Paid holidays
Paid sick leave
Vacation time
Paid family leave

Visa sponsorship

Not detected in the job text

Keywords

Layout Design
High-speed Connectivity
Analog Circuits
CMOS
BiCMOS
SERDES
DAC
ADC
Transimpedance Amplifiers
Modulator Drivers
Floor-planning
Physical Verification
Electromigration
PERC
ESD
Cadence Virtuoso
Mentor Calibre
Synopsys
MPW
Test Chips
Design Rules
Pcells
Scripting
Semiconductor
Networking Infrastructure

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