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Added 7 mins ago
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Ciena

Senior Physical Design Engineer

Ottawa, ON, Canada

Pay: Salary Range: The salary range for this role in Ottawa is $109, 000 - $174, 000
Job type: Full-time
Posting language: English
Posted: Oct 2, 2026

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Original job description

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being - on and off the job. Connect with a career that matters.

Ciena’s WaveLogic family of products is a cornerstone of our optical fiber transmission solutions, driving innovation and success in the telecommunications industry. As a Digital ASIC Physical Implementation Engineer, you will play a critical role in developing large mixed-signal SoC ASICs targeting advanced technology nodes. Your contributions will directly impact the performance, power efficiency, and area optimization of our industry-leading WaveLogic ASICs.

In this role, you will:

Scope and define the physical architecture of designs, utilizing EDA vendor tools to build, adapt, and maintain a robust flow from netlist to full closure and GDSII generation.

Partner with RTL circuit designers and other layout engineers to create optimal floorplans, design power grids, and clock distribution networks that achieve the best performance and power efficiency.

Navigate and fine-tune EDA tool settings, parameters, and attributes to ensure signoff-quality results with an optimal balance of performance, power, and area (PPA).

Identify and propose alternative implementations, trade-offs, and solutions to achieve lower power consumption and higher performance.

Collaborate with analog designers and ASIC/SoC teams to integrate analog blocks seamlessly into the overall design.

Conduct initial Place & Route trials to refine design and correlation, influencing circuit architecture by working closely with RTL designers and architects to ensure reliable and closable physical design.

Generate and implement timing ECOs to achieve timing closure, as well as functional ECOs to address RTL feature fixes when necessary.

Utilize tools like Formality or Conformal for formal verification, analyzing reports and ensuring design accuracy and integrity.

Write scripts to enhance productivity and efficiency for yourself and other backend engineers. Collaborate with tool and technology vendors to drive fixes, improve workflows, and evaluate new tools and features.

Produce concise status reports at various stages of development, highlighting trade-offs and providing actionable insights.

Resolve timing challenges associated with DFT through scan chain reordering, placement, and CTS constraints.

Run Static Timing Analysis (STA), analyze timing reports, and debug issues related to timing constraints and correlation between P&R and STA tools.

Your expertise in physical design, collaboration with cross-functional teams, and ability to innovate will be instrumental in advancing Ciena’s cutting-edge optical networking solutions.

The Must Haves:

Minimum Bachelor’s degree in Electrical or Computer Engineering, Computer Science or other applicable scientific degree coupled with significant experience in ASIC physical digital design and timing closure

Understanding of the submicron technology nodes full backend ASIC flow and timing/power/area analysis and trade-offs.

Proven experience working with Place&Route tools.

Practical experience developing scripts to automate tasks throughout the backend flow.

Understanding of UPF and SOCV/POCV concepts

Nice to Haves:

Experience in working with multiple power domains

Experience with physical verification (Calibre).

Experience with power integrity (EMIR)

Hand-on experience creating and validating timing constraints

Experience with Static Timing Analysis (STA)

Experience with physical synthesis and full RTL-to-GDS flow using industry-standard EDA tools

Salary Range: The salary range for this role in Ottawa is $109, 000 - $174, 000

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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More about this job

Responsibilities

You will scope and define the physical architecture of mixed-signal SoC ASICs while managing the flow from netlist to GDSII generation. Additionally, you will collaborate with cross-functional teams to optimize power, performance, and area through floorplanning, timing closure, and EDA tool refinement.

Requirements

Candidates must hold at least a Bachelor's degree in Electrical or Computer Engineering or a related field. Significant experience in ASIC physical digital design, timing closure, and proficiency with Place & Route tools are required.

Skills

ASIC physical design
Timing closure
Place & Route
Scripting
UPF
SOCV
POCV
Static Timing Analysis
Physical verification
Power integrity
RTL-to-GDS flow
Formal verification
Floorplanning
Clock distribution networks
Mixed-signal SoC

Benefits

Medical plan
Dental plan
Vision plan
DCPP with company matching
Employee Stock Purchase Program
Employee Assistance Program
Company-paid holidays
Paid sick leave
Vacation time
Paid Family Leave

Visa sponsorship

Not detected in the job text

Keywords

ASIC
Physical Design
SoC
Mixed-signal
WaveLogic
EDA
Netlist
GDSII
RTL
Floorplanning
Power Grid
Clock Distribution
PPA
Place & Route
ECO
Formality
Conformal
Formal Verification
DFT
Scan Chain
STA
Submicron
UPF
SOCV
POCV
Calibre
EMIR
Physical Synthesis
Telecommunications
Optical Networking

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