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Added 2 mins ago
IC
Strategy, Lead
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- Full-time
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Cisco

ASIC Development Technical Leader

Vancouver, BC, Canada

Full-time

Apply About employer

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Job details

Job type: Full-time
Apply by: Dec 9, 2026
Posting language: English
Posted: Nov 9, 2026

Original job description

The application window is expected to close on: 12/31/2026

Meet the Team

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms - like Silicon One - are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development - from design to qualification to production - is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact

Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; Handson experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization.
Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.
Proficiency in low-power design methodologies using UPF
Work with Foundry and standard cell IP vendors to define the signoff methodologies and validate/adjust them when you receive feedback from Post-Silicon Validation teams
Experience in using AI tools to improve productivity

Minimum Qualifications

Bachelor’s Degree in Electrical Engineering with 8+ years of Physical Design experience or Master’s Degree in Electrical Engineering with 6+ years of Physical Design experience, or PhD in Electrical Engineering with 3+ years of Physical Design experience.
Experience with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process technologies.
Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus.

Preferred Qualifications

Experience working on Fullchip activities; including floor-planning, power-grid planning, partitioning and pin-assignment.
Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis.
Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
Experience with custom clock (H-Tree or Mesh) at chip level.
Experience with Python and usage of AI tools by giving accurate prompts

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees On Sales Plans Earn Performance-based Incentive Pay On Top Of Their Base Salary, Which Is Split Between Quota And Non-quota Components, Subject To The Applicable Cisco Plan. For Quota-based Incentive Pay, Cisco Typically Pays As Follows

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area

$186,900.00 - $307,800.00

Non-Metro New York State & Washington State

$166,300.00 - $274,100.00

For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

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More about this job

Responsibilities

Lead full-chip floorplanning and hierarchical RTL-to-GDSII implementation, including partitioning, pin assignment, clock and bump planning, power-grid planning, timing analysis, and physical verification. Improve design flows and signoff methodologies while collaborating with system, package, RTL, DFT, EDA, foundry, and standard-cell IP teams to optimize performance, power, and die size.

Requirements

Requires a bachelor's degree in electrical engineering with 8+ years of physical design experience, a master's degree with 6+ years, or a PhD with 3+ years. Candidates need RTL-to-GDSII and tapeout experience at 7nm, 5nm, 3nm, or smaller, plus experience with EDA tools; full-chip design, timing closure, power integrity, custom clocking, Python, and AI tools are preferred.

Skills

ASIC Physical Design
Full-Chip Floorplanning
RTL-to-GDSII Implementation
Hierarchical Design
Clock Mesh and H-Tree Design
Timing Closure
Static Timing Analysis
Power Integrity Analysis
Power Grid Planning
Place and Route
Physical Verification
Low-Power Design
UPF
Python
AI Tools
EDA Tools

Benefits

Medical Insurance
Dental Insurance
Vision Insurance
401(k) Matching
Paid Parental Leave
Short-Term Disability Coverage
Long-Term Disability Coverage
Life Insurance
Paid Holidays
Floating Holiday
Birthday Leave
Year-End Holiday Shutdown
Personal Wellness Days
Paid Vacation
Sick Leave
Family Emergency Leave
Volunteer Leave
Annual Bonuses
Restricted Stock Units

Visa sponsorship

Not detected in the job text

Keywords

ASIC
Physical Design
Full-Chip Floorplanning
RTL-to-GDSII
Design Tapeout
7nm
5nm
3nm
Hierarchical Implementation
Partitioning
Pin Assignment
Clock Mesh
Flex-HTree
H-Tree
Power Grid Planning
Place and Route
Static Timing Analysis
Timing Constraints
Timing Closure
Power Integrity
Physical Verification
Equivalence Checks
UPF
Innovus
Tempus
PrimeTime
RedHawk
Voltus
Calibre
Pegasus

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