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Utility Solar Technician II - Sarnia, ON Canada
NovaSource Power Services
Sarnia, ON
- $48 to $55 CAD / hour
- Full-time
Must have a strong safety background with experience in Lockout Tag Out and Job Hazard Analysis
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Method Technician - Finishing
Safran
Mirabel, QC
- Full-time
Lead and participate in continuous improvement projects aimed at enhancing quality, productivity, costs, and operational performance.
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Coaticook, QC
- Full-time
Lead continuous improvement initiatives related to product engineering changes (CHIPP).
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Magog, QC
- Full-time
Lead continuous improvement initiatives related to product engineering changes (CHIPP).
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Senior Manager, Brands Consulting
THE·TEAM
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- Full-time
Lead detailed program and partnership evaluation, utilizing proprietary and industry measurement tools
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Lead continuous improvement initiatives related to product engineering changes (CHIPP).
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Lead Operator (Agriculture) - Central Ontario FS - Ayr, ON
Central Ontario FS
Ayr, ON
- Full-time
The Lead Operator provides assistance for the supervision of grain and/or agronomy operations staff, as well as the day-to-day safe operation and maintenance and/or security of equipment…
Added 3 hours ago
C
ASIC Development Technical Leader
Cisco
Vancouver, BC
- Full-time
You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend…
Added 3 hours ago
IS
Maintenance Supervisor
Irving Shipbuilding
Halifax, NS
- Full-time
Must have the ability to work effectively with Computerized Maintenance Management System
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Port Coquitlam, BC
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Excellent Benefits package and RRSP/TFSA Program.
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Utility Arborist (Residential)
The Davey Tree Expert Company
Vancouver, BC
- Full-time
Excellent Benefits package and RRSP/TFSA Program.
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Lead Instructor, Digital Marketing
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Director of Repair Operation
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Montreal, QC
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Lead initiatives to resolve non-conformance and audit findings within required timelines.
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Controller / Contrôleur(e)
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Kirkland, QC
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In-office position with the option of one day per week working from home
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Community Relations Program Director
Johns Hopkins All Children's Hospital
Brampton, ON · Regional Municipality of Peel, ON
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Develop and lead the community relations strategy for the health system/hospital, including vision, priorities, standards, workflows, and scalable processes that support enterprise-wide…
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Global Methods Engineer - Machining
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Mirabel, QC
- Full-time
Day shift, Monday to Friday, 38 hours per week
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Senior Compensation Partner, Sales & Marketing
Autodesk
Toronto, ON · Greater Toronto Area, Canada
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Highway Field Inspector
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Added 3 hours ago
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Access Analyst
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Project Coordinator
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AB · Edmonton, AB
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Cisco

ASIC Development Technical Leader

Vancouver, BC, Canada

Full-time

Apply on LinkedIn About employer

Applications open in a new tab.

Job details

Job type: Full-time
Apply by: Dec 10, 2026
Posting language: English
Posted: Nov 10, 2026

Original job description

The application window is expected to close on: 11/23/2026

Meet the Team

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development - from design to qualification to production - is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact

You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team, you will also be involved in crafting groundbreaking next-generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

Minimum Qualifications

Bachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC Design experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or PhD in Electrical Engineering or Computer Engineering + 3 years of ASIC Design experience
Prior experience with scan insertion
Prior experience with ATPG and EDA tools like Tessent tool sets
Prior experience working with Gate level simulation, including timing-based simulations with Standard Delay Format (SDF), debugging with VCS and other simulators
Post-silicon validation and debug experience; Ability to work with ATE engineers on pattern translation and validation

Preferred Qualifications

Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification
Prior experience with Jtag protocols (p1500, p1687)
Scripting skills: Tcl, Python/Perl
Prior experience with test static timing analysis constraints development and timing closure
Prior experience with SSN

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees On Sales Plans Earn Performance-based Incentive Pay On Top Of Their Base Salary, Which Is Split Between Quota And Non-quota Components, Subject To The Applicable Cisco Plan. For Quota-based Incentive Pay, Cisco Typically Pays As Follows

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area

$186,900.00 - $307,800.00

Non-Metro New York State & Washington State

$166,300.00 - $274,100.00

For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

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More about this job

Responsibilities

Lead design-for-test requirements and quality processes across the ASIC implementation flow, collaborating with RTL and physical design teams from early architecture through post-silicon validation. Contribute to next-generation networking chip development and support physical design signoff activities.

Requirements

Requires a bachelor's degree in electrical or computer engineering and at least 8 years of ASIC design experience, a master's degree and at least 6 years, or a PhD and at least 3 years. Candidates need experience with scan insertion, ATPG and Tessent, gate-level timing simulation and debugging, post-silicon validation, and ATE pattern translation; preferred qualifications include Verilog, JTAG protocols, scripting, test timing constraints, timing closure, and SSN.

Skills

ASIC Design
Design-for-Test
Scan Insertion
ATPG
Tessent
Gate-Level Simulation
Standard Delay Format
VCS
Post-Silicon Validation
ATE Pattern Translation
Verilog
JTAG
Tcl
Python
Perl
Static Timing Analysis

Benefits

Medical Insurance
Dental Insurance
Vision Insurance
401(k) With Employer Matching
Paid Parental Leave
Short-Term Disability Coverage
Long-Term Disability Coverage
Life Insurance
Paid Holidays
Floating Holiday
Birthday Leave
Year-End Holiday Shutdown
Personal Wellness Days
Paid Vacation
Flexible Vacation
Sick Leave
Paid Family Emergency Leave
Paid Volunteer Days
Annual Bonus
Restricted Stock Units

Visa sponsorship

Not detected in the job text

Keywords

ASIC
Design-for-Test
ASIC Implementation
Scan Insertion
ATPG
Tessent
Gate-Level Simulation
Standard Delay Format
VCS
Post-Silicon Validation
ATE
Pattern Translation
Verilog
RTL
Physical Design
JTAG
IEEE 1500
IEEE 1687
Tcl
Python
Perl
Static Timing Analysis
Timing Closure
SSN
Networking Chips
Silicon One
ASIC Design
Design Signoff

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Jobs in Canada