Jobs in Ajax, ON and nearby (11,255 jobs)

Jobs within 25 km of Ajax, ON, Canada. Nearby towns and cities are included. Distances are straight-line, not driving distances.

11,255 listings · 1,917 employers Counted Nov 8, 2026. How we count

About these jobs

Employers hiring include Shoppers Drug Mart (316 listings), Loblaw Companies Limited (273 listings), Walmart Canada (227 listings).

Common roles: Retail sales associate, Personal support worker, Practical nurse.

1,665 of these listings include employer-provided pay. Open a job to see its currency and pay period.

Advertised starting pay
Pay period	Median starting pay	Listings
CAD / hour	22.00	825
CAD / year	75,000.00	755

Employer-listed minimums from at least 10 listings per currency and pay period. These are advertised starting amounts, not employee salaries. Jobs without a minimum and unusual amounts are excluded.

Workplace classifications: 0% remote, 15% hybrid, 85% on-site, 0% not specified. Hybrid and on-site classifications may be inferred from descriptions. Check the original ad.

Based on the dated count above. Listings can change. How we count

Jobs in Ajax, ON and nearby

Within 25 km

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Added 3 days ago
SD
Cashier, Hourly Part Time Flexible Shifts
Shoppers Drug Mart
Toronto, ON
- Part-time
Added 3 days ago
Retail Specialist Pickering Town Centre
Freedom Mobile
Pickering, ON
Added 3 days ago
AVP, Direct Distribution and Affinity (Personal Lines)
Aviva
Markham, ON
Added 3 days ago
A
Registered Nurse AgeCare Samac
AgeCare
Oshawa, ON
- Part-time
Added 3 days ago
GF
Overnight Customer Service Representative (Motivator) – Scarborough Kingston and Eglinton
GoodLife Fitness
Toronto, ON
- Part-time
Added 3 days ago
GF
Club Attendant - Whitby Centrum
GoodLife Fitness
Whitby, ON
- Part-time
Added 3 days ago
GV
Lead Project Manager – Grid Automation
GE Vernova
Markham, ON
- $110,100 to $165,200 CAD / year
- Full-time
Added 3 days ago
CA
Data Engineering & Platforms Manager
Canadian Addiction Treatment Centres (CATC)
Markham, ON
- Full-time
Added 3 days ago
Registration & Financial Aid Assistant
University of Toronto
Toronto, ON
Added 3 days ago
A
Engineering Manager, Reactor Engineering
AtkinsRéalis
Pickering, ON
- Full-time
Added 3 days ago
SV
Food Service Aide (FSA) RH, Part-Time with Unscheduled Hours, (Int/Ext)
Schlegel Villages
Whitby, ON
- Part-time
Added 3 days ago
BM
Warehouse Associate I
Benjamin Moore & Co
Whitby, ON
- $22.7 to $30 CAD / hour
- Other
Added 3 days ago
PI
Senior System Architect
PeopleToGo Inc.
Markham, ON
- $105 to $110 CAD / hour
- Contract
Added 3 days ago
SF
Oshawa Automotive Installer
Safe Fleet
Oshawa, ON
- Full-time
Added 3 days ago
TG
Planet Fitness - Member Services Representative - Full Time - Oshawa
Taymax Group
Oshawa, ON
- Full-time
Added 3 days ago
Sales Associate
JD Sports / Livestock / Size?
Toronto, ON
Added 3 days ago
LH
2600002910 - Service Associate
Lakeridge Health
Oshawa, ON
- Internship
Added 3 days ago
BV
Media Sales Representative
Best Version Media
Toronto, ON
- Full-time
Added 3 days ago
BV
Media Sales Representative
Best Version Media
Markham, ON
- Full-time
Added 3 days ago
BV
Media Sales Representative
Best Version Media
Ajax, ON
- Full-time
Added 3 days ago
L
5747 - Seasonal Sales Help
Lids
Oshawa, ON
- $17.95 CAD / hour
- Temporary
Added 3 days ago
L
7703 - Seasonal Sales Help
Lids
Markham, ON
- $17.95 CAD / hour
- Temporary
Added 3 days ago
2I
Cloud Infrastructure Engineer
2iSolutions Inc.
Oshawa, ON
- $70 to $75 CAD / hour
- Contract
Added 3 days ago
BV
Media Sales Representative
Best Version Media
Oshawa, ON
- Full-time
Added 3 days ago
BV
Media Sales Representative
Best Version Media
Pickering, ON
- Full-time

Dexian

Design Engineer

Markham, ON, Canada

$85 to $90 CAD / hour · Contract

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Job details

Pay: $85 to $90 CAD / hour
Job type: Contract
Apply by: Dec 4, 2026
Posting language: English
Posted: Nov 4, 2026

Original job description

Job Title -ASIC/RTL Design Engineer 5#1023342

Duration: 12 Months

Location –Markham ON

THE ROLE:

In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements.

THE PERSON:

You are passionate about digital design, power optimization, and timing closure in advanced semiconductor technologies. You enjoy solving challenging problems, are detail-oriented, and thrive in a collaborative team environment and passionate to work with vibrant team located in different time zone . With strong analytical skills and a methodical approach, you are eager to learn, share knowledge, and contribute to building cutting-edge silicon.

KEY RESPONSIBILITIES:

Develop and implement power reduction strategies across SoC/IP design.
Perform synthesis and static timing analysis (STA) to achieve PPA targets.
Analyze and optimize dynamic and leakage power using industry-standard tools.
Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.
Run low-power verification checks (UPF/CPF) and validate correct power intent implementation.
Support sign-off activities for Lint , CDC , synthesis, timing, and power closure.
Automate and streamline power and timing workflows to improve efficiency.
Build test plan documentation, accounting for interactions with other features, the hardware.

PREFERRED EXPERIENCE:

Strong background in ASIC synthesis and static timing analysis (STA).
Hands-on expertise with EDA tools such as Synopsys Design Compiler, PrimeTime, PrimePower, Power Artists , or equivalent.
Experience with power analysis and optimization techniques (clock gating, multi-Vt, power gating, multi-voltage design).
Familiarity with UPF/CPF power intent specification and verification.
Solid understanding of digital design fundamentals, RTL coding (Verilog/SystemVerilog).
Experience with advanced process nodes (e.g., 7nm, 5nm, 3nm) is a strong plus.
Proficiency in scripting languages (TCL, Perl, Python, or Shell) for flow automation.
Exposure to floorplanning, place-and-route, and ECO flows is desirable.
Knowledge of low-power design methodologies and trade-offs.
Prior leadership, mentorship, or cross-functional collaboration experience is an asset.
Experienced with Verilog, System Verilog, C, and C++
Graphics pipeline knowledge
Automating workflows in a distributed compute environment.

About Dexian: Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of the largest technology and professional staffing companies and one of the largest minority-owned staffing companies in the United States, Dexian combines over 30 years of industry expertise with cutting-edge technologies to deliver comprehensive global services and support.

Dexian connects the right talent and the right technology with the right organizations to deliver trajectory-changing results that help everyone achieve their ambitions and goals.

To learn more, please visit https://dexian.com/.

Dexian is an Equal Opportunity Employer that recruits and hires qualified candidates without regard to race, religion, sex, sexual orientation, gender identity, age, national origin, ancestry, citizenship, disability, or veteran status.

Note: Dexian Canada will, on request, provide accommodations for disabilities to support

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More about this job

Responsibilities

Develop low-power strategies and perform synthesis, static timing analysis, and power optimization to meet SoC and IP design targets. Collaborate with RTL, physical design, and verification teams on power-intent checks, sign-off, workflow automation, and test-plan documentation.

Requirements

The role seeks strong ASIC synthesis and static timing analysis experience, hands-on familiarity with industry EDA tools, and knowledge of low-power techniques and UPF/CPF. It also calls for RTL skills in Verilog/SystemVerilog, scripting for automation, and cross-functional collaboration; advanced-node experience and exposure to physical-design flows are desirable.

Skills

ASIC Synthesis
Static Timing Analysis
Low-Power Design
Power Optimization
RTL Design
Verilog
SystemVerilog
UPF/CPF
EDA Tools
Timing Closure
Power, Performance, And Area Optimization
TCL
Perl
Python
Shell Scripting
Graphics Pipeline

Visa sponsorship

Not detected in the job text

Keywords

ASIC
RTL Design
SoC
IP Design
Synthesis
Static Timing Analysis
Timing Closure
Low-Power Design
Power Optimization
Power, Performance, And Area
Synopsys Design Compiler
PrimeTime
PrimePower
Power Artists
UPF
CPF
Clock Gating
Multi-Vt
Power Gating
Multi-Voltage Design
Verilog
SystemVerilog
C
C++
TCL
Perl
Python
Shell Scripting
Lint
CDC

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