Jobs in Markham, ON and nearby (21,502 jobs)

Jobs within 25 km of Markham, ON, Canada. Nearby towns and cities are included. Distances are straight-line, not driving distances.

21,502 listings · 3,843 employers Counted Nov 6, 2026. How we count

About these jobs

Employers hiring include Loblaw Companies Limited (421 listings), Shoppers Drug Mart (396 listings), Walmart Canada (333 listings).

Common roles: Retail sales associate, Project manager, Personal support worker.

4,066 of these listings include employer-provided pay. Open a job to see its currency and pay period.

Advertised starting pay
Pay period	Median starting pay	Listings
CAD / hour	22.26	2,096
CAD / year	75,000.00	1,800
CAD / month	4,250.00	12

Employer-listed minimums from at least 10 listings per currency and pay period. These are advertised starting amounts, not employee salaries. Jobs without a minimum and unusual amounts are excluded.

Workplace classifications: 0% remote, 17% hybrid, 83% on-site, 0% not specified. Hybrid and on-site classifications may be inferred from descriptions. Check the original ad.

Based on the dated count above. Listings can change. How we count

Jobs in Markham, ON and nearby

Within 25 km

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Added 22 hours ago
OE
General Labourer - Floater
OSI Electronics
Toronto, ON
- $18 CAD / hour
- Full-time
Added 23 hours ago
W
Senior Cost Analyst
Worley
Markham, ON
- Full-time
Added 23 hours ago
Q
FY27 Intern - Telemetry Firmware, Driver and Tools Developer Internship - Canada (16 months)
Qualcomm
Markham, ON
- Full-time
Added 23 hours ago
E
Specialist I, IT Enterprise GIS Technical Specialist
Enbridge
Toronto, ON
- Full-time
Added 23 hours ago
PL
Lifestyle and Programming Manager
Prima Living
Aurora, ON
- Full-time
Added 23 hours ago
PL
Health & Wellness Manager
Prima Living
Aurora, ON
- Full-time
Added 1 day ago
TN
Outside Sales Reps
True North Pest Control
Markham, ON
- Full-time
Added 1 day ago
Seasonal Retail Sales Associate, Scarborough Town Centre
Bell
Toronto, ON
Added 1 day ago
W
Senior Mechanical Engineer
Worley
Markham, ON
- Full-time
Added 1 day ago
W
Manager I, Inside Sales
Worley
Markham, ON
- Full-time
Added 1 day ago
M
Senior Finance Manager, AI Business Solutions
Microsoft
Goodwood, ON
- Full-time
Added 1 day ago
Q
Software Engineer, Machine Learning
Qualcomm
Markham, ON
- Full-time
Added 1 day ago
WC
Sales Representative (Metal) - Vaughan, ON
Wurth Canada
Markham, ON
- Full-time
Added 1 day ago
SE
Google Ads Specialist
Search Engine People Inc.
Pickering, ON
- $60,000 to $80,000 CAD / year
- Full-time
Added 1 day ago
YO
Lifeguard & Swim Instructor
YMCA of Greater Toronto
Markham, ON
- Part-time
Added 1 day ago
D
Senior Product Manager, Echo MS
Danaher
Concord, ON
- $130,000 to $150,000 CAD / year
- Full-time
Added 1 day ago
W-
310T Mechanic (4x10) Mon to Thur day shift
WORKFORCE - Staffing Solutions
Vaughan, ON
- Full-time
Added 1 day ago
PG
Project Manager, Technical Services & High Voltage
Plan Group Inc.
Vaughan, ON
- Full-time
Added 1 day ago
WC
(CAN) Overnight Associate - Temporary 3 Months Contract
Walmart Canada
Richmond Hill, ON
- Contract
Added 1 day ago
WC
(CAN) Stock Unloader Associate
Walmart Canada
Toronto, ON
- Contract
Added 1 day ago
WC
(CAN) Food & Consumables Team Associate
Walmart Canada
Toronto, ON
- Contract
Added 1 day ago
E
Territory Representative, Hospitality Sales & Service
Ecolab
Richmond Hill, ON
- Full-time
Added 1 day ago
RB
Sales Trainee - Contract
Red Bull
Toronto, ON
- Contract
Added 1 day ago
EN
General Manager of Restaurants (Full-Time) - Eataly Yorkville
Eataly North America
Toronto, ON
- $90,000 to $100,000 CAD / year
- Full-time
Added 1 day ago
B
Senior Financial Analyst
BGIS
Markham, ON
- Full-time

Dexian

Design Engineer

Markham, ON, Canada

$85 to $90 CAD / hour · Contract

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Job details

Pay: $85 to $90 CAD / hour
Job type: Contract
Apply by: Dec 4, 2026
Posting language: English
Posted: Nov 4, 2026

Original job description

Job Title -ASIC/RTL Design Engineer 5#1023342

Duration: 12 Months

Location –Markham ON

THE ROLE:

In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements.

THE PERSON:

You are passionate about digital design, power optimization, and timing closure in advanced semiconductor technologies. You enjoy solving challenging problems, are detail-oriented, and thrive in a collaborative team environment and passionate to work with vibrant team located in different time zone . With strong analytical skills and a methodical approach, you are eager to learn, share knowledge, and contribute to building cutting-edge silicon.

KEY RESPONSIBILITIES:

Develop and implement power reduction strategies across SoC/IP design.
Perform synthesis and static timing analysis (STA) to achieve PPA targets.
Analyze and optimize dynamic and leakage power using industry-standard tools.
Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.
Run low-power verification checks (UPF/CPF) and validate correct power intent implementation.
Support sign-off activities for Lint , CDC , synthesis, timing, and power closure.
Automate and streamline power and timing workflows to improve efficiency.
Build test plan documentation, accounting for interactions with other features, the hardware.

PREFERRED EXPERIENCE:

Strong background in ASIC synthesis and static timing analysis (STA).
Hands-on expertise with EDA tools such as Synopsys Design Compiler, PrimeTime, PrimePower, Power Artists , or equivalent.
Experience with power analysis and optimization techniques (clock gating, multi-Vt, power gating, multi-voltage design).
Familiarity with UPF/CPF power intent specification and verification.
Solid understanding of digital design fundamentals, RTL coding (Verilog/SystemVerilog).
Experience with advanced process nodes (e.g., 7nm, 5nm, 3nm) is a strong plus.
Proficiency in scripting languages (TCL, Perl, Python, or Shell) for flow automation.
Exposure to floorplanning, place-and-route, and ECO flows is desirable.
Knowledge of low-power design methodologies and trade-offs.
Prior leadership, mentorship, or cross-functional collaboration experience is an asset.
Experienced with Verilog, System Verilog, C, and C++
Graphics pipeline knowledge
Automating workflows in a distributed compute environment.

About Dexian: Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of the largest technology and professional staffing companies and one of the largest minority-owned staffing companies in the United States, Dexian combines over 30 years of industry expertise with cutting-edge technologies to deliver comprehensive global services and support.

Dexian connects the right talent and the right technology with the right organizations to deliver trajectory-changing results that help everyone achieve their ambitions and goals.

To learn more, please visit https://dexian.com/.

Dexian is an Equal Opportunity Employer that recruits and hires qualified candidates without regard to race, religion, sex, sexual orientation, gender identity, age, national origin, ancestry, citizenship, disability, or veteran status.

Note: Dexian Canada will, on request, provide accommodations for disabilities to support

Apply About employer

More about this job

Responsibilities

Develop low-power strategies and perform synthesis, static timing analysis, and power optimization to meet SoC and IP design targets. Collaborate with RTL, physical design, and verification teams on power-intent checks, sign-off, workflow automation, and test-plan documentation.

Requirements

The role seeks strong ASIC synthesis and static timing analysis experience, hands-on familiarity with industry EDA tools, and knowledge of low-power techniques and UPF/CPF. It also calls for RTL skills in Verilog/SystemVerilog, scripting for automation, and cross-functional collaboration; advanced-node experience and exposure to physical-design flows are desirable.

Skills

ASIC Synthesis
Static Timing Analysis
Low-Power Design
Power Optimization
RTL Design
Verilog
SystemVerilog
UPF/CPF
EDA Tools
Timing Closure
Power, Performance, And Area Optimization
TCL
Perl
Python
Shell Scripting
Graphics Pipeline

Visa sponsorship

Not detected in the job text

Keywords

ASIC
RTL Design
SoC
IP Design
Synthesis
Static Timing Analysis
Timing Closure
Low-Power Design
Power Optimization
Power, Performance, And Area
Synopsys Design Compiler
PrimeTime
PrimePower
Power Artists
UPF
CPF
Clock Gating
Multi-Vt
Power Gating
Multi-Voltage Design
Verilog
SystemVerilog
C
C++
TCL
Perl
Python
Shell Scripting
Lint
CDC

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