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Added 27 mins ago
AA
Software Engineer IV, Viper Engineering
ACV Auctions
Toronto, ON
- Full-time
ACV Auctions is looking for a Software Engineer to join our ACV Retail - Viper Teams and work on our SaaS Product. The position will focus on backend development & maintenance of Go Lang…
Added 27 mins ago
T
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- Full-time
Career progression into Senior Test Analyst, QA Engineer, Automation Engineer, QA Lead, or QA Manager roles.
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Senior Software Engineer
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Added 42 mins ago
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MC
Cloud Platform Engineer – Kubernetes (36051)
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Added 42 mins ago
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Production Support Engineer
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Added 42 mins ago
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AI/ML Platform Engineer – Containers & GPU Infrastructure - Canada
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Added 42 mins ago
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Embedded C++ Software Engineer
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Added 57 mins ago
Software Engineer IV, Viper Engineering
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Added 57 mins ago
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Senior IT Systems Engineer
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- $150,000 to $185,000 CAD / year
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Added 57 mins ago
2I
Cloud Infrastructure Engineer
2iSolutions Inc.
Oshawa, ON
- $70 to $75 CAD / hour
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Added 57 mins ago
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Field Service Engineer
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Added 57 mins ago
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Full Stack Engineer
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Added 57 mins ago
D
Design Engineer
Dexian
Markham, ON
- $85 to $90 CAD / hour
- Contract
Job Title -ASIC/RTL Design Engineer 5#1023342
Added 57 mins ago
MQ
Software Automation Engineer
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Markham, ON
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Tantalus is seeking an early-career Analytics Engineer to join our Customer Operations team, reporting to the Senior Director, Customer Experience.
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We are seeking a senior Professional Engineer who has built the majority of their career around hydraulic and hydrologic modelling and is motivated by developing both high-quality models…
Added 1 hour ago
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Added 1 hour ago
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Added 1 hour ago
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Title: DevOps Platform Engineer (Terraform/EKS)

Dexian

Design Engineer

Markham, ON, Canada

$85 to $90 CAD / hour · Contract

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Job details

Pay: $85 to $90 CAD / hour
Job type: Contract
Apply by: Dec 4, 2026
Posting language: English
Posted: Nov 4, 2026

Original job description

Job Title -ASIC/RTL Design Engineer 5#1023342

Duration: 12 Months

Location –Markham ON

THE ROLE:

In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements.

THE PERSON:

You are passionate about digital design, power optimization, and timing closure in advanced semiconductor technologies. You enjoy solving challenging problems, are detail-oriented, and thrive in a collaborative team environment and passionate to work with vibrant team located in different time zone . With strong analytical skills and a methodical approach, you are eager to learn, share knowledge, and contribute to building cutting-edge silicon.

KEY RESPONSIBILITIES:

Develop and implement power reduction strategies across SoC/IP design.
Perform synthesis and static timing analysis (STA) to achieve PPA targets.
Analyze and optimize dynamic and leakage power using industry-standard tools.
Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.
Run low-power verification checks (UPF/CPF) and validate correct power intent implementation.
Support sign-off activities for Lint , CDC , synthesis, timing, and power closure.
Automate and streamline power and timing workflows to improve efficiency.
Build test plan documentation, accounting for interactions with other features, the hardware.

PREFERRED EXPERIENCE:

Strong background in ASIC synthesis and static timing analysis (STA).
Hands-on expertise with EDA tools such as Synopsys Design Compiler, PrimeTime, PrimePower, Power Artists , or equivalent.
Experience with power analysis and optimization techniques (clock gating, multi-Vt, power gating, multi-voltage design).
Familiarity with UPF/CPF power intent specification and verification.
Solid understanding of digital design fundamentals, RTL coding (Verilog/SystemVerilog).
Experience with advanced process nodes (e.g., 7nm, 5nm, 3nm) is a strong plus.
Proficiency in scripting languages (TCL, Perl, Python, or Shell) for flow automation.
Exposure to floorplanning, place-and-route, and ECO flows is desirable.
Knowledge of low-power design methodologies and trade-offs.
Prior leadership, mentorship, or cross-functional collaboration experience is an asset.
Experienced with Verilog, System Verilog, C, and C++
Graphics pipeline knowledge
Automating workflows in a distributed compute environment.

About Dexian: Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of the largest technology and professional staffing companies and one of the largest minority-owned staffing companies in the United States, Dexian combines over 30 years of industry expertise with cutting-edge technologies to deliver comprehensive global services and support.

Dexian connects the right talent and the right technology with the right organizations to deliver trajectory-changing results that help everyone achieve their ambitions and goals.

To learn more, please visit https://dexian.com/.

Dexian is an Equal Opportunity Employer that recruits and hires qualified candidates without regard to race, religion, sex, sexual orientation, gender identity, age, national origin, ancestry, citizenship, disability, or veteran status.

Note: Dexian Canada will, on request, provide accommodations for disabilities to support

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More about this job

Responsibilities

Develop low-power strategies and perform synthesis, static timing analysis, and power optimization to meet SoC and IP design targets. Collaborate with RTL, physical design, and verification teams on power-intent checks, sign-off, workflow automation, and test-plan documentation.

Requirements

The role seeks strong ASIC synthesis and static timing analysis experience, hands-on familiarity with industry EDA tools, and knowledge of low-power techniques and UPF/CPF. It also calls for RTL skills in Verilog/SystemVerilog, scripting for automation, and cross-functional collaboration; advanced-node experience and exposure to physical-design flows are desirable.

Skills

ASIC Synthesis
Static Timing Analysis
Low-Power Design
Power Optimization
RTL Design
Verilog
SystemVerilog
UPF/CPF
EDA Tools
Timing Closure
Power, Performance, And Area Optimization
TCL
Perl
Python
Shell Scripting
Graphics Pipeline

Visa sponsorship

Not detected in the job text

Keywords

ASIC
RTL Design
SoC
IP Design
Synthesis
Static Timing Analysis
Timing Closure
Low-Power Design
Power Optimization
Power, Performance, And Area
Synopsys Design Compiler
PrimeTime
PrimePower
Power Artists
UPF
CPF
Clock Gating
Multi-Vt
Power Gating
Multi-Voltage Design
Verilog
SystemVerilog
C
C++
TCL
Perl
Python
Shell Scripting
Lint
CDC

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