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Added 1 min ago
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Full-time
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Added 1 min ago
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Added 17 mins ago
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Added 17 mins ago
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Diligent Tec, Inc

Senior Design Verification Engineer

Vancouver, BC, Canada

Job type: Contract
Apply by: Oct 30, 2026
Posting language: English
Posted: Sep 30, 2026

Apply About employer

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Original job description

Company Description Diligent Tec, Inc. is a technology consulting firm specializing in advanced semiconductor and electronic design services. The company partners with leading organizations to deliver high-quality engineering solutions across the full product development lifecycle. Diligent Tec, Inc. focuses on complex digital design and verification challenges, offering expertise in cutting-edge architectures and verification methodologies. Team members collaborate in a technically rigorous environment that values precision, innovation, and continuous learning. The company supports flexible work models to attract and retain highly skilled engineering professionals.

We are looking for an experienced Design Verification Engineer for a contract role with one of our direct clients in Vancouver, BC.

Canadian Citizens, PR holders, and candidates with valid Canadian Work Permits are encouraged to apply. US Citizens who are currently in the USA and are genuinely willing to spend the initial 1 month in Vancouver.

Job Title: Design Verification Engineer

Experience: 6+ - 15

Location: Vancouver, BC, Canada - Initial 1 month Hybrid then after Remote

Job Type: Contract

Job Summary

We are looking for a Design Verification Engineer with strong experience in ASIC/SoC verification to develop and execute verification environments and ensure high-quality digital designs.

Responsibilities

Develop verification environments and testbenches using SystemVerilog and UVM.
Create and execute functional, regression, and constrained-random tests.
Analyze functional/code coverage and drive coverage closure.
Debug RTL and simulation failures and work with design teams to resolve issues.
Verify protocols such as AMBA/AXI, PCIe, Ethernet, or similar interfaces.
Automate testing and regression using Python, Perl, or Shell scripting.

Required Skills

Strong SystemVerilog & UVM experience.
Solid understanding of RTL, digital design, and ASIC/SoC verification.
Experience with simulation tools such as VCS, Xcelium, or Questa.
Strong debugging and scripting skills.
Bachelor's/Master's degree in Electrical, Electronics, or Computer Engineering.

Interested/available? Please reply with your updated resume + the following:

Name:

Current Location:

Work Authorization:

Years of Experience:

Relevant DV Experience:

Availability:

Expected Rate:

Phone:

Apply About employer

More about this job

Responsibilities

Develop SystemVerilog and UVM verification environments and testbenches, and create and run functional, regression, and constrained-random tests. Analyze coverage, debug RTL and simulation failures, verify interfaces such as AMBA/AXI, PCIe, and Ethernet, and automate testing and regressions with scripting.

Requirements

Requires strong SystemVerilog and UVM experience, a solid understanding of RTL, digital design, and ASIC/SoC verification, and experience with VCS, Xcelium, or Questa. Candidates should have strong debugging and scripting skills and a bachelor's or master's degree in Electrical, Electronics, or Computer Engineering.

Skills

SystemVerilog
UVM
ASIC/SoC Verification
RTL
Digital Design
Verification Environments
Testbench Development
Functional Testing
Regression Testing
Constrained-Random Testing
Functional Coverage
Code Coverage
Debugging
AMBA/AXI
PCIe
Ethernet

Visa sponsorship

Not detected in the job text

Keywords

SystemVerilog
UVM
ASIC
SoC
RTL
Digital Design
Design Verification
Verification Environment
Testbench
Functional Testing
Regression Testing
Constrained-Random Testing
Functional Coverage
Code Coverage
Coverage Closure
VCS
Xcelium
Questa
AMBA
AXI
PCIe
Ethernet
Python
Perl
Shell Scripting
Simulation
Debugging
Electrical Engineering
Electronics Engineering
Computer Engineering

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