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ELITS

PCB Layout Developer

Ottawa, ON, K1P 1A5, Canada

Job type: Full-time
Posting language: English
Posted: Sep 30, 2026

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Original job description

About ELITS

ELITS Canada Inc. is part of Accelerate, within the IVER Group in Sweden. IVER Group has approximately 1,300 employees and continues to grow. Through Accelerate, we work at the forefront of technology on digitization and transformation projects for market leading customers. We help customers turn digital ambition into successful implementation through close collaboration, humility, and pride in what we deliver.

ELITS is now looking for an experienced PCB Layout Developer to join our dynamic team.

Key Responsibilities:

PCB Layout Development: Lead and execute PCB layout activities for high‑speed, multi‑layer digital and mixed‑signal boards.
Constraint Management: Apply and manage layout constraints using Cadence tools, particularly Allegro Constraint Manager (ACM), ensuring signal integrity, power integrity, and compliance.
Schematic Review: Collaborate with digital designers to review and validate front‑end constraints and schematics.
Design Optimization: Optimize component placement and routing for electrical performance, thermal efficiency, and mechanical requirements.
Documentation: Produce and maintain layout documentation, including Gerber files, assembly drawings, and fabrication outputs.
Quality Assurance: Perform DRC and ERC checks and participate in design reviews.
Cross‑Functional Collaboration: Work closely with multidisciplinary teams to align layout activities with system‑level requirements and project timelines.

Qualifications:

Diploma or degree in Electrical Engineering, Electronics Technology, or a related field.
Five or more years of experience in PCB layout design, preferably in telecom or embedded systems.

Technical Skills:

Proficiency with Cadence layout tools, especially Allegro and ACM.
Strong understanding of high‑speed design principles, impedance control, and EMI/EMC best practices.
Experience reviewing and applying front‑end design constraints.
Solid knowledge of PCB materials, stack‑up design, and manufacturability considerations.
Familiarity with IPC standards and PCB fabrication processes.

Required Skills:

Experience with DDRx memory interfaces, SerDes technologies, and power distribution networks.
Deep understanding of signal integrity (SI) and power integrity (PI), especially during early placement and routing planning.
Ability to manage multiple layout projects and meet tight deadlines.
Strong communication and documentation skills.

Qualities:

Communicative, positive, and customer‑oriented.
Strong analytical skills, logical reasoning, and problem‑solving abilities.
Responsible, autonomous, and resourceful.
Team‑oriented, organized, and committed to quality results.
Creative and proactive, with ideas to improve products and processes.
Able to coordinate and handle multiple tasks simultaneously.

Are you a social, flexible, and structured person with a great interest in information technology? Do you find development, constructing, and use of the latest technologies challenging? In that case – send your application to us today!

This position is open to Canadian residents (persons with work permit in Canada).

ELITS - Part of Accelerate at Iver Group

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More about this job

Responsibilities

The PCB Layout Developer will lead and execute layout activities for high-speed, multi-layer digital and mixed-signal boards. They will also collaborate with multidisciplinary teams to ensure design optimization, signal integrity, and compliance with project requirements.

Requirements

Candidates must hold a diploma or degree in Electrical Engineering or a related field with at least five years of experience in PCB layout design. Proficiency in Cadence Allegro and a strong understanding of high-speed design principles and IPC standards are required.

Skills

PCB Layout
Cadence Allegro
Allegro Constraint Manager
High-speed design
Signal integrity
Power integrity
Impedance control
EMI/EMC
DDRx memory interfaces
SerDes
Power distribution networks
Gerber files
DRC
ERC
Stack-up design
IPC standards

Visa sponsorship

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Keywords

PCB Layout
Cadence
Allegro
Constraint Manager
High-speed design
Signal integrity
Power integrity
Mixed-signal
Gerber
DRC
ERC
DDRx
SerDes
EMI
EMC
Stack-up
IPC standards
Telecom
Embedded systems
Electrical engineering
Electronics technology
Fabrication
Assembly drawings
Thermal efficiency
Digitization

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