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Ethernovia, Inc.

Senior ASIC (Front End) Design Engineer

Toronto, ON, Canada

Experience: Minimum 10+ years of ASIC RTL design and/or architecture experience
Posting language: English
Posted: Sep 28, 2026

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Original job description

About Ethernovia, Inc.

Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakthrough data transport and acceleration technology is ushering in a new era of connectivity and capabilities in the vehicle and at the edge, including highly reliable autonomy, over-the-air servicing and AI-backed applications.

Ethernovia's co-founders are serial technology entrepreneurs with multiple prior successful ventures together. We are well-funded and backed by some of the worlds’ leading technology investors, having secured $154M ($90+M Series-B and $64M Series-A) in total funding to date:

Ethernovia Raises Over $90 Million Series B to Scale Leading-Edge Autonomy and Physical AI Networking Chips
Ethernovia Raises $64 Million to Accelerate the Revolution of Vehicle Networks | Business Wire
- (financial backers include: Porsche SE, Qualcomm, AMD, Western Digital, Maverick Silicon, Socratic Partners, Conduit Capital, and CDIB-TEN Capital)

Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025.

With talented employees on 4 continents, we have filed 50+ patents to date.

Join Ethernovia’s team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive cutting edge designs from concept to silicon to the future of mobility.

Senior ASIC (Front End) Design Engineer

Summary:

As a Senior ASIC (Front End) Design Engineer, you will be responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals.
Work with system architects, software, hardware, and verification engineers to plan, architect, design, implement, and deliver advanced automotive communication semiconductors and systems.
You will be on the leading edge of the development and definition of advanced, high-performance custom silicon that embodies functions from a wide range of protocols, algorithms, and applications.
Expected to flesh out product definitions with precise specifications of: an ASIC's internal and external interactions, data flow, processing algorithms across a number of disciplines, resource management, and software interfaces.
You will be a trusted self-starter who can work with very little guidance or oversight.
This position is located in: Toronto, Canada - Hybrid

Key Qualifications:

BS and/or MS in Electrical Engineering, Computer Science, or related field
Minimum 10+ years of ASIC RTL design and/or architecture experience
Proven track record with the development of complex SoCs
Strong understanding of digital design fundamentals and methodologies
In-depth knowledge of Verilog/System Verilog and simulation tools.
Self-motivated and able to work effectively both independently and in a team

Additional Success Factors:

Experience in any of the following areas:

Networking (Ethernet MAC, PHY/PCS, Switching, TCP/IP, PCIe and other industry standard protocols)
Digital signal processing filters
Digital Mixed-Signal modeling, design, and integration
IP integration (SerDes, controllers, processors, etc.)
Video standards, protocols, processing
Perl, TCL, C/C++, Make

Personal Skills:

Excellent communication/documentation skills.
Attention to details.
Collaboration across multidisciplinary and international teams.

What You Can Expect from Ethernovia:

Technology depth and breadth expansion that can’t be found in a large company
Opportunity to grow your career as the company grows
Pre IPO stock options
Cutting edge technology
World class team
Competitive base salary
Flexible hours
Medical, dental and vision insurance for employees

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More about this job

Responsibilities

You will be responsible for all aspects of digital SoC design, including micro-architecture, RTL, verification, and static timing analysis. You will collaborate with cross-functional teams to architect and deliver advanced automotive communication semiconductors.

Requirements

Candidates must have a BS or MS in Electrical Engineering or Computer Science with at least 10 years of ASIC RTL design experience. Strong proficiency in Verilog/System Verilog and a proven track record in complex SoC development are required.

Skills

ASIC design
RTL design
System Verilog
Verilog
SoC design
Micro-architecture
Verification
Synthesis
Static timing analysis
CDC
Networking
Digital signal processing
IP integration
TCL
C++
Perl

Benefits

Pre-IPO stock options
Competitive compensation
Medical insurance
Dental insurance
Vision insurance
Flexible hours

Visa sponsorship

Not detected in the job text

Keywords

ASIC
SoC
RTL
Verilog
System Verilog
Networking
Ethernet
PCIe
Digital Signal Processing
IP Integration
TCL
C++
Perl
Automotive
Semiconductors
Micro-architecture
Static Timing Analysis
CDC
LEC
Physical AI
Autonomous Vehicles
Robotics
7nm
NVIDIA Holoscan
Packet Processor

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