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HCLTech

Design Verification Engineer

  • Canada

Full-time

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Job details

Job type
Full-time
Posting language
English
Posted

Original job description

JD::

ASIC Programs (Switch/NIC) DV

  • Lead or contribute to verification of 4–5 ASIC design blocks.
  • Develop UVM-based verification environments, sequences, tests, debug, and coverage closure.
  • Strong experience in SystemVerilog/UVM.
  • Experience with PCIe, UCIe 2.0, and Ethernet protocols.
  • Ability to independently own verification deliverables.
  • Support customer collaboration in EST timezone.

Required Skills

  • Strong SystemVerilog/UVM verification experience
  • Knowledge and/or hands-on experience with:
  • UCIe 2.0
  • PCIe
  • Ethernet
  • Ability to own design blocks independently and drive verification closure

Responsibilities

The DV team is expected to:

  • Own verification of 4–5 design blocks per ASIC
  • Develop and execute sequences
  • Perform test development and debug
  • Drive coverage collection and closure
  • Own end-to-end verification execution for assigned blocks
  • The customer will own the testbench infrastructure.
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More about this job

Responsibilities

The Design Verification Engineer will own the verification of 4-5 ASIC design blocks, including developing sequences and driving coverage closure. They are responsible for end-to-end verification execution and supporting customer collaboration in the EST timezone.

Requirements

Candidates must have strong experience in SystemVerilog and UVM verification environments. Hands-on experience with PCIe, UCIe 2.0, and Ethernet protocols is required to independently own verification deliverables.

Skills

  • SystemVerilog
  • UVM
  • ASIC Design
  • PCIe
  • UCIe 2.0
  • Ethernet
  • Verification Environment Development
  • Test Development
  • Debug
  • Coverage Closure
  • Design Block Verification

Visa sponsorship

Not detected in the job text

Categories

  • Technology
  • Engineering
  • Software

Keywords

  • ASIC
  • Design Verification
  • SystemVerilog
  • UVM
  • PCIe
  • UCIe 2.0
  • Ethernet
  • Verification Environment
  • Testbench
  • Coverage Closure
  • Debug
  • Hardware Verification
  • Switch
  • NIC
  • Semiconductor

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