Design Verification Engineer (PCIe)
- Canada
Full-time
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Job details
- Job type
- Full-time
- Posting language
- English
- Posted
Original job description
🚀 Hiring: Design Verification Engineer (PCIe) | Canada
Are you passionate about cutting-edge semiconductor and high-speed interface technologies? We are looking for a Design Verification (DV) Engineer with strong expertise in SystemVerilog (SV), UVM, and PCIe verification to join a dynamic engineering team.
Key Responsibilities:
✅ Design and develop robust verification environments using SystemVerilog and UVM
✅ Verify PCIe Gen3/Gen4/Gen5 protocols and ensure compliance with specifications
✅ Develop reusable verification components, testbenches, and methodologies
✅ Create and maintain assertions (SVA), coverage models, and constrained-random test scenarios
✅ Debug complex design and protocol issues and drive them to closure
✅ Collaborate closely with design and architecture teams
Required Skills:
- Strong experience in Design Verification using SystemVerilog (SV) and UVM
- Hands-on experience in PCIe Gen3/Gen4/Gen5 protocol verification
- Strong understanding of:
- PCIe Architecture
- LTSSM
- Transaction Layer
- Data Link Layer
- Physical Layer
- Exposure to AXI, APB, and AHB protocols
- Experience developing reusable verification environments and VIPs
- Knowledge of SVA, coverage-driven verification, and constrained-random methodologies
- Experience with simulators such as VCS, Xcelium, or Questa
- Excellent debugging, analytical, and problem-solving skills
📩 Interested candidates can apply directly or send their updated resume. Connect with me to learn more!
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More about this job
Responsibilities
Develop reusable SystemVerilog and UVM verification environments, testbenches, components, assertions, coverage models, and constrained-random tests for PCIe Gen3/Gen4/Gen5. Debug design and protocol issues, ensure specification compliance, and collaborate with design and architecture teams.
Requirements
Requires strong design verification experience with SystemVerilog and UVM, plus hands-on verification of PCIe Gen3, Gen4, or Gen5 and understanding of PCIe architecture and its protocol layers. Candidates should also have exposure to AXI, APB, and AHB, experience with reusable verification environments and VIPs, knowledge of SVA and coverage-driven methods, and familiarity with VCS, Xcelium, or Questa.
Skills
- SystemVerilog
- UVM
- PCIe Verification
- PCIe Gen3/Gen4/Gen5
- PCIe Architecture
- LTSSM
- Transaction Layer
- Data Link Layer
- Physical Layer
- AXI
- APB
- AHB
- SystemVerilog Assertions
- Coverage-Driven Verification
- Constrained-Random Verification
- Debugging
Visa sponsorship
Not detected in the job text
Categories
- Engineering
- Technology
- Software
Keywords
- Design Verification
- SystemVerilog
- UVM
- PCIe
- PCIe Gen3
- PCIe Gen4
- PCIe Gen5
- PCIe Architecture
- LTSSM
- Transaction Layer
- Data Link Layer
- Physical Layer
- AXI
- APB
- AHB
- Verification Components
- Testbenches
- Verification IP
- SystemVerilog Assertions
- Coverage Models
- Coverage-Driven Verification
- Constrained-Random Testing
- VCS
- Xcelium
- Questa
- Semiconductors
- ASIC
- SoC
- Protocol Verification