Full-time jobs in Canada (383,481 jobs)

Explore full-time jobs across Canada. Choose a location and read the full job details.

383,481 listings · 47,460 employers Counted Nov 10, 2026. How we count

About these jobs

Employers hiring include Walmart Canada (9,105 listings), Health Match BC (4,035 listings), Walmart (2,932 listings).

Common roles: Project manager, Sales representative, Cook.

67,149 of these listings include employer-provided pay. Open a job to see its currency and pay period.

Advertised starting pay
Pay period	Median starting pay	Listings
CAD / hour	24.00	39,170
CAD / year	80,000.00	25,639
CAD / month	5,347.31	700
USD / year	127,500.00	226
CAD / week	1,530.00	77
CAD / day	360.00	44
USD / hour	22.00	28
GBP / year	40,000.00	13
EUR / year	68,000.00	11
USD / month	4,000.00	11

Employer-listed minimums from at least 10 listings per currency and pay period. These are advertised starting amounts, not employee salaries. Jobs without a minimum and unusual amounts are excluded.

Workplace classifications: 1% remote, 16% hybrid, 82% on-site, 0% not specified. Hybrid and on-site classifications may be inferred from descriptions. Check the original ad.

Based on the dated count above. Listings can change. How we count

Full-time jobs in Canada

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INNOSILICON

Intermediate/Senior Digital IC Design Engineer

Ottawa, ON, Canada

Full-time

Apply on LinkedIn About employer

Applications open in a new tab.

Job details

Job type: Full-time
Apply by: Dec 10, 2026
Experience: 5 years of relevant digital FPGA/ASIC/IC design experience
Posting language: English
Posted: Nov 10, 2026

Original job description

Innosilicon is seeking to hire an Intermediate/Senior Digital IC Design Engineer to join our Inter-connectivity Memory Business Unit. The successful candidate will work with our experienced global engineering team developing market-leading SerDes IP products. We look forward to welcoming talented engineers on our journey.

Responsibilities

Design specification: Help write block-level design specifications, run system-level simulations, and support chip-level architecture definition and documentation.
Implementation: Develop RTL in Verilog and take blocks through lint, clock domain crossing (CDC) analysis, synthesis, static timing analysis, timing closure, and top-level integration. Support DFT tasks.
Verification: Work with the verification team on test planning and execution, debug block- and system-level simulations, and support formal verification.
Flow and methodology: Help develop and improve the design flows and methods used across our interdisciplinary R&D group.
Validation and production: Work with the validation and production teams to create test plans and test vectors that ensure product quality and robustness.

Qualifications

Proactive, curious and eager to learn, great attention to details, positive, and great team work
Bachelor's or Master's Degree in Electrical or Computer Engineering
5 years of relevant digital FPGA/ASIC/IC design experience
Significant experience with RTL coding in Verilog/SystemVerilog
Significant experience with standard ASIC software tools (lint, clock domain crossing analysis, timing constraints, synthesis, simulation, logical equivalence checking, DFT, static timing analysis)
Strong knowledge of Python scripting, Linux/Unix environment, and basic C/C++ programming
Strong knowledge of PCIe, Ethernet
Thorough understanding of ASIC design flow
Design-for-verification experience or understanding (assertion-based design strategies, code coverage, functional coverage, test plans etc.) would be an asset
Self-starter and fast learner with excellent interpersonal skills
Track record of driving technical solutions across organizational boundaries and multiple technical disciplines
Proficiency in Chinese would be considered an asset

Apply on LinkedIn About employer

More about this job

Responsibilities

Develop and integrate RTL blocks for SerDes IP products, including design specifications, system-level simulation, lint, CDC analysis, synthesis, timing closure, and top-level integration. Collaborate with verification, validation, production, and architecture teams on testing, formal verification, DFT support, and improvements to design flows and methodologies.

Requirements

Requires a bachelor's or master's degree in Electrical or Computer Engineering and five years of relevant digital FPGA, ASIC, or IC design experience, with significant Verilog/SystemVerilog and standard ASIC tool experience. Candidates should have strong Python and Linux/Unix skills, basic C/C++ knowledge, familiarity with PCIe and Ethernet, and a thorough understanding of ASIC design flow; design-for-verification experience and Chinese proficiency are assets.

Skills

Verilog
SystemVerilog
RTL Design
ASIC Design
FPGA Design
Lint
Clock Domain Crossing Analysis
Synthesis
Static Timing Analysis
Timing Closure
Design for Test
Formal Verification
Python
Linux/Unix
PCIe
Ethernet

Visa sponsorship

Not detected in the job text

Keywords

SerDes IP
Digital IC Design
ASIC
FPGA
RTL
Verilog
SystemVerilog
Lint
Clock Domain Crossing
Synthesis
Static Timing Analysis
Timing Closure
Top-Level Integration
Design for Test
Formal Verification
System-Level Simulation
Logical Equivalence Checking
Timing Constraints
Python
Linux/Unix
C/C++
PCIe
Ethernet
Design for Verification
Assertion-Based Design
Code Coverage
Functional Coverage
ASIC Design Flow
Validation
Semiconductor Manufacturing

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Work requirements

Full-time jobs in Canada